A clustering-based algorithm for zero-skew clock routing with buffer insertion

ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549) ◽

10.1109/icasic.2001.982527 ◽

2002 ◽

Author(s):

Yi Liu ◽

Meng Zhao ◽

Xianlong Hong ◽

Yici Cai ◽

Weimin Wu

Keyword(s):

Buffer Insertion ◽

Clock Routing ◽

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A zero-skew clock routing scheme for VLSI circuits

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1992.279328 ◽

1992 ◽

Author(s):

Li ◽

Jabri

Keyword(s):

Vlsi Circuits ◽

Routing Scheme ◽

Clock Routing ◽

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A single layer zero skew clock routing in X architecture

Science in China Series F Information Sciences ◽

10.1007/s11432-009-0028-6 ◽

2009 ◽

Vol 52 (8) ◽

pp. 1466-1475 ◽

Author(s):

WeiXiang Shen ◽

YiCi Cai ◽

XianLong Hong ◽

Jiang Hu ◽

Bing Lu

Keyword(s):

Single Layer ◽

Clock Routing ◽

X Architecture ◽

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Zero-skew clock routing trees with minimum wirelength

[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1992.270316 ◽

2003 ◽

Author(s):

K.D. Boese ◽

A.B. Kahng

Keyword(s):

Clock Routing ◽

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An algorithm for zero-skew clock tree routing with buffer insertion

Proceedings ED&TC European Design and Test Conference ◽

10.1109/edtc.1996.494154 ◽

2002 ◽

Author(s):

Y.P. Chen ◽

D.F. Wong

Keyword(s):

Buffer Insertion ◽

Tree Routing ◽

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Zero skew clock routing for fast clock tree generation

The International Conference on Electrical Engineering ◽

10.21608/iceeng.2008.34322 ◽

2008 ◽

Vol 6 (6) ◽

pp. 1-11

Author(s):

M. Reaz ◽

M. Ibrahimy ◽

F. Mohd-Yasin ◽

A. Mohammad

Keyword(s):

Tree Generation ◽

Clock Routing ◽

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Zero skew clock routing in multiple-clock synchronous systems

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1992.279327 ◽

1992 ◽

Author(s):

Khan ◽

Hossain ◽

Sherwani

Keyword(s):

Synchronous Systems ◽

Clock Routing ◽

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Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture

8th International Symposium on Quality Electronic Design (ISQED'07) ◽

10.1109/isqed.2007.120 ◽

2007 ◽

Author(s):

Weixiang Shen ◽

Yici Cai ◽

Xianlong Hong ◽

Jiang Hu ◽

Bing Lu

Keyword(s):

Single Layer ◽

Clock Routing ◽

X Architecture ◽

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Zero skew clock routing with minimum wirelength

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing ◽

10.1109/82.204128 ◽

1992 ◽

Vol 39 (11) ◽

pp. 799-814 ◽

Author(s):

Ting-Hai Chao ◽

Yu-Chin Hsu ◽

Jan-Ming Ho ◽

A.B. Kahng

Keyword(s):

Clock Routing ◽

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An exact zero-skew clock routing algorithm

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.205004 ◽

1993 ◽

Vol 12 (2) ◽

pp. 242-249 ◽

Author(s):

R.-S. Tsay

Keyword(s):

Routing Algorithm ◽

Clock Routing ◽

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Zero Skew Clock-Tree Optimization With Buffer Insertion/Sizing and Wire Sizing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2004.825875 ◽

2004 ◽

Vol 23 (4) ◽

pp. 565-572 ◽

Author(s):

J.-L. Tsai ◽

T.-H. Chen ◽

C.C.-P. Chen

Keyword(s):

Buffer Insertion ◽

Tree Optimization ◽

Wire Sizing ◽

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