8th International Symposium on Quality Electronic Design (ISQED'07)
Latest Publications

TOTAL DOCUMENTS

171

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H-INDEX

(FIVE YEARS 0)

Published By IEEE

0769527957

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Power Delivery Aware Floorplanning for Voltage Island Designs

8th International Symposium on Quality Electronic Design (ISQED'07) ◽

10.1109/isqed.2007.121 ◽

2007 ◽

Cited By ~ 7

Author(s):

Yici Cai ◽

Bin Liu ◽

Jin Shi ◽

Qiang Zhou ◽

Xianlong Hong

Keyword(s):

Power Delivery

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Processing High Volume Scan Test Results for Yield Learning

8th International Symposium on Quality Electronic Design (ISQED'07) ◽

10.1109/isqed.2007.126 ◽

2007 ◽

Cited By ~ 4

Author(s):

Alfred L. Crouch ◽

Phil Burlison ◽

Dennis Ciplickas

Keyword(s):

High Volume ◽

Test Results ◽

Scan Test ◽

Yield Learning

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SilcVerify: An Efficient Substrate Coupling Noise Simulation Tool for High-Speed&Nano-Scaled Memory Design

8th International Symposium on Quality Electronic Design (ISQED'07) ◽

10.1109/isqed.2007.144 ◽

2007 ◽

Cited By ~ 2

Author(s):

Jeong-Yeol Kim ◽

Ho-Soon Shin ◽

Jong-Bae Lee ◽

Moon-Hyun Yoo ◽

Jeong-Taek Kong

Keyword(s):

High Speed ◽

Simulation Tool ◽

Memory Design ◽

Coupling Noise ◽

Substrate Coupling ◽

Noise Simulation

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Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure

8th International Symposium on Quality Electronic Design (ISQED'07) ◽

10.1109/isqed.2007.91 ◽

2007 ◽

Cited By ~ 2

Author(s):

Yu-Min Kuo ◽

Cheng-Hung Lin ◽

Chun-Yao Wang ◽

Shih-Chieh Chang ◽

Pei-Hsin Ho

Keyword(s):

Random Vector ◽

Probability Analysis ◽

Circuit Structure

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Tests on Symmetry and Continuity between BSIM4 and BSIM5

8th International Symposium on Quality Electronic Design (ISQED'07) ◽

10.1109/isqed.2007.157 ◽

2007 ◽

Author(s):

Xudong Niu ◽

Yan Song ◽

Bo Li ◽

Wei Bian ◽

Yadong Tao ◽

...

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An Efficient Algorithm for RLC Buffer Insertion

8th International Symposium on Quality Electronic Design (ISQED'07) ◽

10.1109/isqed.2007.33 ◽

2007 ◽

Cited By ~ 1

Author(s):

Zhanyuan Jiang ◽

Shiyan Hu ◽

Jiang Hu ◽

Weiping Shi

Keyword(s):

Efficient Algorithm ◽

Buffer Insertion

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Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture

8th International Symposium on Quality Electronic Design (ISQED'07) ◽

10.1109/isqed.2007.81 ◽

2007 ◽

Cited By ~ 2

Author(s):

Rajsekhar Adapa ◽

Edward Flanigan ◽

Spyros Tragoudas ◽

Michael Laisne ◽

Hailong Cui ◽

...

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults

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InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization

8th International Symposium on Quality Electronic Design (ISQED'07) ◽

10.1109/isqed.2007.94 ◽

2007 ◽

Cited By ~ 4

Author(s):

Kai-hui Chang ◽

David A. Papa ◽

Igor L. Markov ◽

Valeria Bertacco

Keyword(s):

Similarity Metrics ◽

Verification System

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High-Frequency-Measurement-Based Frequency-Variant Transmission Line Characterization and Circuit Modeling for Accurate Signal Integrity Verification

8th International Symposium on Quality Electronic Design (ISQED'07) ◽

10.1109/isqed.2007.87 ◽

2007 ◽

Cited By ~ 1

Author(s):

Hyunsik Kim ◽

Yungseon Eo

Keyword(s):

Transmission Line ◽

High Frequency ◽

Signal Integrity ◽

Frequency Measurement ◽

Circuit Modeling ◽

Integrity Verification

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Impact of Variability on Clock Skew in H-tree Clock Networks

8th International Symposium on Quality Electronic Design (ISQED'07) ◽

10.1109/isqed.2007.88 ◽

2007 ◽

Cited By ~ 12

Author(s):

Ashok Narasimhan ◽

Ramalingam Sridhar

Keyword(s):

Clock Skew ◽

Clock Networks

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8th International Symposium on Quality Electronic Design (ISQED'07)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Power Delivery Aware Floorplanning for Voltage Island Designs

Processing High Volume Scan Test Results for Yield Learning

SilcVerify: An Efficient Substrate Coupling Noise Simulation Tool for High-Speed&Nano-Scaled Memory Design

Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure

Tests on Symmetry and Continuity between BSIM4 and BSIM5

An Efficient Algorithm for RLC Buffer Insertion

Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture

InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization

High-Frequency-Measurement-Based Frequency-Variant Transmission Line Characterization and Circuit Modeling for Accurate Signal Integrity Verification

Impact of Variability on Clock Skew in H-tree Clock Networks

8th International Symposium on Quality Electronic Design (ISQED'07)
Latest Publications