A novel high performance distributed arithmetic adaptive filter implementation on an FPGA

2004 ◽  
Author(s):  
D.J. Allred ◽  
Heejong Yoo ◽  
V. Krishnan ◽  
W. Huang ◽  
D.V. Anderson
Keyword(s):  
Adaptive Filter ◽  
High Performance ◽  
Distributed Arithmetic

Two High-Performance Adaptive Filter Implementation Schemes Using Distributed Arithmetic

2011 ◽  
Vol 58 (9) ◽  
pp. 600-604 ◽  
Author(s):  
Rui Guo ◽  
Linda S. DeBrunner
Keyword(s):  
Adaptive Filter ◽  
High Performance ◽  
Distributed Arithmetic

A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits

2019 ◽  
Vol 66 (1) ◽  
pp. 313-326 ◽  
Author(s):  
Honglan Jiang ◽  
Leibo Liu ◽  
Pieter P. Jonker ◽  
Duncan G. Elliott ◽  
Fabrizio Lombardi ◽  
...  
Keyword(s):  
Adaptive Filter ◽  
Energy Efficient ◽  
High Performance ◽  
Arithmetic Circuits ◽  
Distributed Arithmetic

Energy Efficient VLSI Based DCT Architecture with Accurate Error Compensation

2014 ◽  
Vol 626 ◽  
pp. 127-135 ◽  
Author(s):  
D. Jessintha ◽  
M. Kannan ◽  
P.L. Srinivasan
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Time Complexity ◽  
High Performance ◽  
Low Power Consumption ◽  
Distributed Arithmetic ◽  
Technology Scaling ◽  
Truncation Errors ◽  
History Of ◽  
Technology Dependency

Discrete Cosine Transform (DCT) is commonly used in image compression. In the history of DCT, a milestone was the Distributed Arithmetic (DA) technique. Due to the technology dependency a multiplier-less computation was built with DA based technique. It occupied less area but the throughput is less. Later, due to the technology scaling, multiplier based architectures can be easily adapted for low-power and high-performance architecture. Fixed width multipliers [1]-[7] reduces hardware and time complexity. In this work, Radix 4 fixed width multiplier is adapted with DCT architecture due to low power consumption and saves 30% power. In order to reduce truncation errors caused during fixed width multiplication, an estimation circuit is designed based on conditional probability theory.

scholarly journals FPGA based least mean square algorithm for noise cancellation in communication system

2018 ◽  
Vol 7 (3.3) ◽  
pp. 165
Author(s):  
Praveen Reddy ◽  
Dr Baswaraj Gadgay
Keyword(s):  
Adaptive Filter ◽  
Communication System ◽  
Noise Cancellation ◽  
Mean Square ◽  
Least Mean Square ◽  
Distributed Arithmetic ◽  
Negative Effect ◽  
Least Mean Square Algorithm ◽  
Design Comparison

We present modified Distributed Arithmetic (DA) based architecture for LMS Adaptive filter which has improved the throughput of the filter also area and power has been comparatively been reduced. As we know, the adaptive filter uses continuous recalculation and generation of new coefficients will generate the negative effect on the use of algorithm. We have used a special temporary LUT addressing technique has overcome the issues resulting in better performance and good results. In this paper, we have discussed about the adaptive filter and implementation of DA adaptive filter and also discussed the results obtained from the design. Comparison with traditional de-sign has also been done to show the effectiveness of the algorithm.   

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