Energy Efficient VLSI Based DCT Architecture with Accurate Error Compensation

2014 ◽  
Vol 626 ◽  
pp. 127-135 ◽  
Author(s):  
D. Jessintha ◽  
M. Kannan ◽  
P.L. Srinivasan

Discrete Cosine Transform (DCT) is commonly used in image compression. In the history of DCT, a milestone was the Distributed Arithmetic (DA) technique. Due to the technology dependency a multiplier-less computation was built with DA based technique. It occupied less area but the throughput is less. Later, due to the technology scaling, multiplier based architectures can be easily adapted for low-power and high-performance architecture. Fixed width multipliers [1]-[7] reduces hardware and time complexity. In this work, Radix 4 fixed width multiplier is adapted with DCT architecture due to low power consumption and saves 30% power. In order to reduce truncation errors caused during fixed width multiplication, an estimation circuit is designed based on conditional probability theory.

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.


Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 223 ◽  
Author(s):  
Yannan Zhang ◽  
Ke Han ◽  
and Jiawei Li

Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.


2015 ◽  
Vol 793 ◽  
pp. 549-553
Author(s):  
Muhammad Bilal Sarwar ◽  
N. Perumal ◽  
Zuhairi Baharudin ◽  
Mohana Sundaram Muthuvalu

A low power, cost effective and energy efficient microcontroller (PIC 16F877A) based transceiver model has been presented. The designed model entails a combination of programmable microcontroller and relay circuitry to control the robotic vehicle through transceiver module. The model was simulated in a Mikro C environment, for communication signals from controlling side. The simulation results show an energy efficiency of 73%, with a distance of 20 meters for robotic vehicle. The results are in good agreement with theoretical understandings and show a greater efficiency, with low power consumption and reduced complexity. The simulations are found recurrent with stable findings and deemed compatible for applications.


2013 ◽  
Vol 333-335 ◽  
pp. 2412-2416
Author(s):  
Jin Feng Yan ◽  
Ming Deng ◽  
Yan Jun Li ◽  
Qi Sheng Zhang

SoPC technology is a high-performance, low-power consumption embedded system solution based on embedded microprocessor, providing a new way for developing new type centralized engineering seismograph. The paper presents the development of a new type centralized engineering seismograph based on SoPC technology, which adopts FPGA design based on SoPC technology for the hardware design and embedded software program development of the 48-channel engineering seismograph. According to actual needs of currently available centralized engineering seismograph, combining the actual characteristics of SoPC embedded technology, a portable, low-power consumption and high-performance new type centralized engineering seismograph is constructed. The paper describes the hardware design and software program implementation of the centralized engineering seismograph in detail.


VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 349-363
Author(s):  
V. A. Bartlett ◽  
E. Grass

Strategies for the design of ultra low power multipliers and multiplier-accumulators are reported. These are optimized for asynchronous applications being able to take advantage of data-dependent computation times. Nevertheless, the low power consumption can be obtained in both synchronous and asynchronous environments. Central to the energy efficiency is a dynamic-logic technique termed Conditional Evaluation which is able to exploit redundancies within the carry-save array and deliver energy consumption which is also heavily data-dependent.Energy efficient adaptations for handling two's complement operands are introduced. Area overheads of the proposed designs are estimated and transistor level simulation results of signed and unsigned multipliers as well as a signed multiplier-accumulator are given.Normalized comparisons with other designs show our approach to use less energy than other published multipliers.


2014 ◽  
Vol 3 (5-6) ◽  
Author(s):  
Tetsuya Kawanishi

AbstractThis paper describes wired and wireless seamless networks consisting of radiowave and optical fiber links. Digital coherent technology developed for high-speed optical fiber transmission can mitigate signal deformation in radiowave links in the air as well as in optical fibers. Radio-over-fiber (RoF) technique, which transmits radio waveforms on intensity envelops of optical signals, can provide direct waveform transfer between optical and radio signals by using optical-to-electric or electric-to-optical conversion devices. Combination of RoF in millimeter-wave bands and digital coherent with high-performance digital signal processing (DSP) can provide wired and wireless seamless links where bit rate of wireless links would be close to 100 Gb/s. Millimeter-wave transmission distance would be shorter than a few kilometers due to large atmospheric attenuation, so that many moderate distance wireless links, which are seamlessly connected to optical fiber networks should be required to provide high-speed mobile-capable networks. In such systems, reduction of power consumption at media converters connecting wired and wireless links would be very important to pursue both low-power consumption and large capacity.


Sign in / Sign up

Export Citation Format

Share Document