Fault Tolerant Architecture Design of a 4-bit Magnitude Comparator

2017 ◽  
Author(s):  
Priti Das ◽  
Apurva Sinha ◽  
Atin Mukherjee
Keyword(s):  
Fault Tolerant ◽  
Architecture Design

scholarly journals Fault-tolerant architecture for Cache : Summaries, Assessments and Trends

2021 ◽  
Vol 2113 (1) ◽  
pp. 012068
Author(s):  
Xuru Wang ◽  
Xin Gao ◽  
Zongnan Liang ◽  
Jiawei Nian ◽  
Hongjin Liu
Keyword(s):  
Fault Tolerance ◽  
Power Consumption ◽  
Future Development ◽  
Fault Tolerant ◽  
Development Trend ◽  
The Other ◽  
Architecture Design ◽  
Related Research ◽  
Cache Architecture ◽  
The Future

Abstract Fault-tolerant design of cache is a key aspect of highly reliable processor design. In this paper, based on the key metrics in Cache architecture design: reliability, power consumption, latency and area, we divided the related research into two categories: one is to maximize reliability with guaranteed latency, power consumption and area, the other is to minimize latency, power consumption and area loss while ensuring fault tolerance reliability. Based on the classification, by analyzing different studies of Data and Tag in Cache, this paper gives the characteristics of these methods and the future development trend.

scholarly journals Architecture Design of Aviation Fault-tolerant Computer Based on ARINC659 Bus Technology

2018 ◽  
Vol 179 ◽  
pp. 03025
Author(s):  
Gang An ◽  
Yu Li ◽  
Xin Li
Keyword(s):  
Fault Tolerance ◽  
Computer Architecture ◽  
Computer System ◽  
Communication Systems ◽  
Fault Tolerant ◽  
High Reliability ◽  
Architecture Design ◽  
Tolerance Mechanism ◽  
Computer Communication ◽  
Computer Based

The ARINC659 backplane bus is suitable for high safety and high reliability requirements of aircraft on-board computer communication systems. This paper analyzes the structure of ARINC 659 serial backplane bus and the bus fault tolerance mechanism. On the basis of backplane bus, a 4 degree of aviation fault-tolerant computer is designed. Moreover, the computer architecture and computer system of the instruction branch and monitoring branch are designed in the computer channel. The fault-tolerant management of the computer is realized by bus fault tolerance, redundancy voting between computers and the monitoring of the instruction and monitoring branches.

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