A technique for low power testing of VLSI chips

2012 International Conference on Devices, Circuits and Systems (ICDCS) ◽

10.1109/icdcsyst.2012.6188654 ◽

2012 ◽

Author(s):

R. Jayagowri ◽

K. S. Gurumurthy

Keyword(s):

Low Power ◽

Low Power Testing ◽

Power Testing ◽

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Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips

Progress in VLSI Design and Test - Lecture Notes in Computer Science ◽

10.1007/978-3-642-31494-0_7 ◽

2012 ◽

pp. 52-58 ◽

Author(s):

R. Jayagowri ◽

K. S. Gurumurthy

Keyword(s):

Low Power ◽

Flip Flop ◽

Low Power Testing ◽

Power Testing ◽

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Efficient scan-based BIST scheme for low power testing of VLSI chips

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design ◽

10.1145/1165573.1165667 ◽

2006 ◽

Author(s):

Malav Shah

Keyword(s):

Low Power ◽

Low Power Testing ◽

Power Testing ◽

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Efficient Scan-Based BIST Scheme for Low Power Testing of VLSI Chips

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design ◽

10.1109/lpe.2006.4271872 ◽

2006 ◽

Author(s):

Malav Shah

Keyword(s):

Low Power ◽

Low Power Testing ◽

Power Testing ◽

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Low Power Testing based on MOS Design Modified Flip-Flop

Indian Journal of Science and Technology ◽

10.17485/ijst/2016/v9i29/91653 ◽

2016 ◽

Vol 9 (29) ◽

Author(s):

Anjali Chava ◽

S. Saravanan

Keyword(s):

Low Power ◽

Flip Flop ◽

Low Power Testing ◽

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Low power testing - What can commercial DFT tools provide?

2011 International Green Computing Conference and Workshops ◽

10.1109/igcc.2011.6008609 ◽

2011 ◽

Author(s):

Xijiang Lin

Keyword(s):

Low Power ◽

Low Power Testing ◽

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A new BIST structure for low power testing

2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03 ◽

10.1109/icasic.2003.1277425 ◽

2003 ◽

Author(s):

Li Jie ◽

Yang Jun ◽

Li Rui ◽

Wang Chao

Keyword(s):

Low Power ◽

Low Power Testing ◽

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An efficient test vector ordering method for low power testing

IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2004.1339559 ◽

2004 ◽

Author(s):

X. Kavousianos ◽

D. Bakalis ◽

M. Bellos ◽

D. Nikolos

Keyword(s):

Low Power ◽

Test Vector ◽

Low Power Testing ◽

Efficient Test ◽

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Is Low Power Testing Necessary? What does the Test Industry Truly Need?

2009 Asian Test Symposium ◽

10.1109/ats.2009.91 ◽

2009 ◽

Author(s):

Anis Uzzaman

Keyword(s):

Low Power ◽

Low Power Testing ◽

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Low power testing using re-configurable Johnson counter and scalable SIC counter

2015 International Conference on Communications and Signal Processing (ICCSP) ◽

10.1109/iccsp.2015.7322754 ◽

2015 ◽

Author(s):

Pallavi Margade

Keyword(s):

Low Power ◽

Low Power Testing ◽

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ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing

14th Asian Test Symposium (ATS'05) ◽

10.1109/ats.2005.72 ◽

2005 ◽

Author(s):

H. Esmaeilzadeh ◽

S. Shamshiri ◽

P. Saeedi ◽

Z. Navabi

Keyword(s):

Low Power ◽

Low Power Testing ◽

Cell Architecture ◽

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