ScienceGate
Advanced Search
Author Search
Journal Finder
Blog
Sign in / Sign up
ScienceGate
Search
Author Search
Journal Finder
Blog
Sign in / Sign up
Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips
Progress in VLSI Design and Test - Lecture Notes in Computer Science
◽
10.1007/978-3-642-31494-0_7
◽
2012
◽
pp. 52-58
◽
Cited By ~ 2
Author(s):
R. Jayagowri
◽
K. S. Gurumurthy
Keyword(s):
Low Power
◽
Flip Flop
◽
Low Power Testing
◽
Power Testing
◽
Vlsi Chips
Download Full-text
Related Documents
Cited By
References
Low Power Testing based on MOS Design Modified Flip-Flop
Indian Journal of Science and Technology
◽
10.17485/ijst/2016/v9i29/91653
◽
2016
◽
Vol 9
(29)
◽
Author(s):
Anjali Chava
◽
S. Saravanan
Keyword(s):
Low Power
◽
Flip Flop
◽
Low Power Testing
◽
Power Testing
Download Full-text
A technique for low power testing of VLSI chips
2012 International Conference on Devices, Circuits and Systems (ICDCS)
◽
10.1109/icdcsyst.2012.6188654
◽
2012
◽
Cited By ~ 1
Author(s):
R. Jayagowri
◽
K. S. Gurumurthy
Keyword(s):
Low Power
◽
Low Power Testing
◽
Power Testing
◽
Vlsi Chips
Download Full-text
Modified Scan Flip-Flop for Low Power Testing
2010 19th IEEE Asian Test Symposium
◽
10.1109/ats.2010.69
◽
2010
◽
Cited By ~ 14
Author(s):
Amit Mishra
◽
Nidhi Sinha
◽
Satdev
◽
Virendra Singh
◽
Sreejit Chakravarty
◽
...
Keyword(s):
Low Power
◽
Flip Flop
◽
Low Power Testing
◽
Power Testing
Download Full-text
A Bypassable Scan Flip-flop for Low Power Testing with Data Retention Capability
IEEE Transactions on Circuits & Systems II Express Briefs
◽
10.1109/tcsii.2021.3096885
◽
2021
◽
pp. 1-1
Author(s):
Xugang Cao
◽
Hailong Jiao
◽
Erik Jan Marinissen
Keyword(s):
Low Power
◽
Data Retention
◽
Flip Flop
◽
Low Power Testing
◽
Power Testing
Download Full-text
Efficient scan-based BIST scheme for low power testing of VLSI chips
ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design
◽
10.1145/1165573.1165667
◽
2006
◽
Author(s):
Malav Shah
Keyword(s):
Low Power
◽
Low Power Testing
◽
Power Testing
◽
Vlsi Chips
Download Full-text
Efficient Scan-Based BIST Scheme for Low Power Testing of VLSI Chips
ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design
◽
10.1109/lpe.2006.4271872
◽
2006
◽
Cited By ~ 1
Author(s):
Malav Shah
Keyword(s):
Low Power
◽
Low Power Testing
◽
Power Testing
◽
Vlsi Chips
Download Full-text
Low power testing - What can commercial DFT tools provide?
2011 International Green Computing Conference and Workshops
◽
10.1109/igcc.2011.6008609
◽
2011
◽
Author(s):
Xijiang Lin
Keyword(s):
Low Power
◽
Low Power Testing
◽
Power Testing
Download Full-text
A new BIST structure for low power testing
2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03
◽
10.1109/icasic.2003.1277425
◽
2003
◽
Cited By ~ 3
Author(s):
Li Jie
◽
Yang Jun
◽
Li Rui
◽
Wang Chao
Keyword(s):
Low Power
◽
Low Power Testing
◽
Power Testing
Download Full-text
An efficient test vector ordering method for low power testing
IEEE Computer Society Annual Symposium on VLSI
◽
10.1109/isvlsi.2004.1339559
◽
2004
◽
Cited By ~ 5
Author(s):
X. Kavousianos
◽
D. Bakalis
◽
M. Bellos
◽
D. Nikolos
Keyword(s):
Low Power
◽
Test Vector
◽
Low Power Testing
◽
Efficient Test
◽
Power Testing
Download Full-text
Is Low Power Testing Necessary? What does the Test Industry Truly Need?
2009 Asian Test Symposium
◽
10.1109/ats.2009.91
◽
2009
◽
Author(s):
Anis Uzzaman
Keyword(s):
Low Power
◽
Low Power Testing
◽
Power Testing
Download Full-text
Sign in / Sign up
Close
Export Citation Format
Close
Share Document
Close