A Comparative Study of Low Power Testing Techniques for Digital Circuits

In recent years, with fast growth of mobile communication and portable computing systems, design for low power has become the challenge in the field of Digital VLSI design. The main focus of the paper is to make a comparative study of low power Linear Feedback Shift Register (LFSR) architecture such as Built In Self Test (BIST), it has been often seen that during test mode process the power consumed is much higher, when compared to that of normal mode process test as there is high switching activity in the nodes of Circuit Under Test(CUT) during testing.