An Ultra Low Power Successive Approximation ADC with Selectable Resolution in 0.13 μm CMOS Technology

2006 ◽  
Author(s):  
A. Arbat ◽  
A. Dieguez ◽  
J. Samitier
Keyword(s):  
Low Power ◽  
Successive Approximation ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Successive Approximation Adc

Ultra-low-power variable-resolution successive approximation ADC for biomedical application

2005 ◽  
Vol 41 (11) ◽  
pp. 634 ◽  
Author(s):  
H.P. Le ◽  
J. Singh ◽  
L. Hiremath ◽  
V. Mallapur ◽  
A. Stojcevski
Keyword(s):  
Low Power ◽  
Successive Approximation ◽  
Biomedical Application ◽  
Ultra Low Power ◽  
Variable Resolution ◽  
Successive Approximation Adc

scholarly journals Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology

2021 ◽  
Vol 9 (VII) ◽  
pp. 3073-3080
Author(s):  
Sarita Chauhan
Keyword(s):  
Low Power ◽  
Successive Approximation ◽  
Cmos Technology ◽  
High Energy ◽  
Sar Adc ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Successive Approximation Adc ◽  
Analog Cmos

After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are popular for achieving high energy efficiency and low power applications. But they suffer from resolution and speed limitation. To overcome the speed limitations of SAR ADC, we proposed the implementation of 90nm using CMOS technology of a low power, high speed pipelined analog-to-digital converter (ADC). The capacitive digital-to-analog converter (DAC), two stage CMOS comparator with output inverter of proposed ADC are lower than those of a conventional ADC. To achieve low power and to minimize the size of the input sampling capacitance in order to ease durability.

An Ultra-Low-Power, 16 Bits CT Delta-Sigma Modulator Using 4-Bit Asynchronous SAR Quantizer for Medical Applications

2019 ◽  
Vol 29 (04) ◽  
pp. 2050056
Author(s):  
Sahel Javahernia ◽  
Esmaeil Najafi Aghdam ◽  
Pooya Torkzadeh
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Digital To Analog Converter ◽  
Ultra Low Power ◽  
Feed Forward ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Summing Amplifier ◽  
Capacitor Structure ◽  
Asynchronous Sar

In this paper, a low-power second-order feed-forward capacitor-structure continuous-time [Formula: see text] modulator with a 4-bit asynchronous successive approximation register (SAR) quantizer is presented. Through the utilization capacitor structure in the proposed modulator, first, the summation node of the integrators’ outputs and the feed-forward signals is implemented within the second integrator to reduce power consumption by eliminating an active summing amplifier. Second, the proposed architecture can compensate for the quantizer delay without using any excess inner digital to analog converter (DAC). In this design, the modulator applies two different low-power operational amplifiers. These advantages cause the modulator to consume very low power and achieve a favorable figure of merit (FOM) value. In fact, in this paper, the combination of the previously reported methods and designs and doing required reforms has led to a new design with better performance, especially in power reduction. The designed modulator which is simulated using 0.18[Formula: see text][Formula: see text]m CMOS technology achieves 95.98[Formula: see text]dB peak signal-to-noise and distortion (SNDR) for 10[Formula: see text]KHz signal bandwidth and dissipates 44[Formula: see text][Formula: see text]w while its FOM is obtained about 43 fJ/conv.-step.

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