10-Bit, 1GS/S Time-Interleaved SAR ADC

This paper describes the implementation of a 4-channel, 10-bit, 1 GS/s time-interleaved analog to digital converter (TI-ADC) in 65nm CMOS technology. Each channel consists of interleaved T/H and ADC array operating at 250 MS/s, with each ADC array containing 14 timeinterleaved sub-ADCs. This configuration provides high sampling rate even though each subADC works at a moderate sampling rate. We have selected 10-bit successive approximation ADC (SAR ADC) as a sub-ADC, since this architecture is most suitable for low power and medium resolution. SAR ADC works on binary search algorithm, since it resolves 1-bit at a time. The target sampling rate was 20 MS/s in this design, however the sampling rate achieved is 15 MS/s. As a result, the 10-bit SAR ADC operates at 15 MS/s with power consumption of 560 μW at 1.2 V supply and achieves SNDR of 57 dB (i.e. ENOB 9.2 bits) near nyquist rate input. The resulting Figure of Merit (FoM) is 63.5 fJ/step. The achieved DNL and INL is +0.85\-0.9 LSB and +1\-1.1 LSB respectively. The 10-bit SAR ADC occupies an active area of 300 μm × 440 μm. The functionality of single channel TI-SAR ADC has been verified by simulation with input signal frequency of 33.2 MHz and clock frequency of 250 MHz. The desired SNDR of 59.3 dB has been achieved with power consumption of 11.6 mW. This results in a FoM value of 60 fJ/step.

Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology

After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are popular for achieving high energy efficiency and low power applications. But they suffer from resolution and speed limitation. To overcome the speed limitations of SAR ADC, we proposed the implementation of 90nm using CMOS technology of a low power, high speed pipelined analog-to-digital converter (ADC). The capacitive digital-to-analog converter (DAC), two stage CMOS comparator with output inverter of proposed ADC are lower than those of a conventional ADC. To achieve low power and to minimize the size of the input sampling capacitance in order to ease durability.

Ten-Bit 0.909-MHz 8-Channel Dual-Mode Successive Approximation ADC for a BLDC Motor Drive

This paper presents a 10-bit 0.909-MHz 8-channel dual-mode successive approximation (SAR) analogue-to-digital converter (ADC) for brushless direct current (BLDC) motor drive, using a Taiwan Semiconductor Manufacturing (TSMC) 0.25 μm 1P3M Complementary Metal Oxide Semiconductor (CMOS) process. The sample-and-hold (S/H) circuit operates with two sampling modes. One is individually sampling eight channels in sequence with an S/H circuit and the other is sampling four channels simultaneously with four S/H circuits. All sampled data will be digitized with high-speed SAR ADC in time division multiplexing (TDM). A dynamic latch-type comparator is utilized to latch the output at an upper or lower level. The advantage of the designed comparator is that it performs with positive feedback to quickly complete the latch function. The double-tail latch-type architecture is utilized to mitigate the significant kickback effect by separating the pre-amplifier stage from the latch. By integrating an input NMOSFET with an input PMOSFET, the designed latch-type comparator can perform with full-swing input voltage. Measurements show that the signal-to-noise ratio (SNR), signal-to-noise-and-distortion ratio (SNDR), effective number of bits (ENOB), power consumption, and chip area are 50.56 dB, 57.03 dB, 8.11 bits, 833 μW, and 1.35 × 0.98 mm2, respectively. The main advantages of the proposed multichannel dual-mode SAR ADC are its low power consumption of 833 μW and high measured resolution of 8.11 bits.

BIT ERROR NOTIFICATION AND ESTIMATION IN REDUNDANT SUCCESSIVE-APPROXIMATION ADC

The article is devoted to research on the possibilities to use redundant number systems for bit error notification in a successive-approximation ADC during the main conversion mode. The transfer function of a successive-approximation ADC with a non-binary radix is analyzed. If the radix is less than 2, not all possible code combinations appear on the converter output. The process of formation of unused combinations is investigated. The relationship between the bit’s deviations and the list of unused combinations is established. The possibilities of estimating the bit error value without interrupting the process of analog-to-digital conversion is considered.

Reconfigurable Analog Preprocessing for Efficient Asynchronous Analog-to-Digital Conversion

Wearable medical devices, wireless sensor networks, and other energy-constrained sensing devices are often concerned with finding specific data within more-complex signals while maintaining low power consumption. Traditional analog-to-digital converters (ADCs) can capture the sensor information at a high resolution to enable a subsequent digital system to process for the desired data. However, traditional ADCs can be inefficient for applications that only require specific points of data. This work offers an alternative path to lower the energy expenditure in the quantization stage—asynchronous content-dependent sampling. This asynchronous sampling scheme is achieved by pairing a flexible analog front-end with an asynchronous successive-approximation ADC and a time-to-digital converter. The versatility and reprogrammability of this system allows a multitude of event-driven, asynchronous, or even purely data-driven quantization methods to be implemented for a variety of different applications. The system, fabricated in standard 0.5 μ m and 0.35 μ m processes, is demonstrated along with example applications with voice, EMG, and ECG signals.