A FDM-based Simultaneous Wireless Power and Data Transfer (SWPDT) System Functioning with High-rate Full-duplex Communication

Author(s):  
Haisong Cheng ◽  
Longlong ZHANG ◽  
Lei Wang ◽  
Yousu Yao ◽  
Jianwei Mai ◽  
...  
2020 ◽  
Vol 16 (10) ◽  
pp. 6370-6381 ◽  
Author(s):  
Yousu Yao ◽  
Haisong Cheng ◽  
Yijie Wang ◽  
Jianwei Mai ◽  
Kaixing Lu ◽  
...  

2018 ◽  
Vol 16 ◽  
pp. 29-34
Author(s):  
Christian Schmidt ◽  
Martin Buchholz ◽  
Madhukar Chandra

Abstract. Short range inductive data transfer has become very popular in the last years with the increased interest in technologies like RFID and NFC. Additionally, wireless power transfer has been a field of intensive research and product development. In industrial applications, a combination of both is often needed to replace mechanical contacts, mainly for safety and reliability reasons, especially regarding spark prevention and maintenance reduction. In this paper, we present a compact inductive structure that can be implemented in an existing wireless energy transfer system. The structure is developed by field considerations, leading to a single structure comprising two signal ports that are decoupled from each other, but can be used to transfer a signal to a second structure of that kind with very small interference. An optimisation to achieve comparable channel characteristics is conducted by using 3-D field simulations. Subsequent measurements are conducted to verify the achieved performance.


2021 ◽  
Vol 69 (1) ◽  
pp. 1161-1175
Author(s):  
Masaya Tamura ◽  
Kousuke Murai ◽  
Marimo Matsumoto
Keyword(s):  

2011 ◽  
Vol 383-390 ◽  
pp. 6840-6845 ◽  
Author(s):  
Yong Hong Gu ◽  
Wei Huang ◽  
Qiao Li Yang

To transmit and receive data over any network successfully, a protocol is required to manage the flow. High-level Data Link Control (HDLC) protocol is defined in Layer 2 of OSI model and is one of the most commonly used Layer 2 protocol. HDLC supports both full-duplex and half-duplex data transfer. In addition, it offers error control and flow control. Currently on the market there are many dedicated HDLC chips, but these chips are neither of control complexity nor of limited number of channels. This paper presents a new method for implementing a multi-channel HDLC protocol controller using Altera FPGA and VHDL as the target technology. Implementing a multi-channel HDLC protocol controller in FPGA offers the flexibility, upgradability and customization benefits of programmable logic and also reduces the total cost of every project which involves HDLC protocol controllers.


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