To deal with the large amount of data and complex computing problems during high-speed image acquisition, the image acquisition and preprocess system based on FPGA is designed in the paper. In order to obtain continuous and integrity of image data streams, the design has completed the acquisition of CCD camera video signal and implementation of de-interlacing ping-pong cache. The fast median filtering algorithm is used for image preprocessing, and finally the preprocessed image data is displayed on CRT. Experiments indicate that the design meets requirements of image sample quality and balances the real-time demand.
