The Design of Image Acquisition and Preprocess System Based on FPGA
2011 ◽
Vol 71-78
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pp. 4269-4273
Keyword(s):
To deal with the large amount of data and complex computing problems during high-speed image acquisition, the image acquisition and preprocess system based on FPGA is designed in the paper. In order to obtain continuous and integrity of image data streams, the design has completed the acquisition of CCD camera video signal and implementation of de-interlacing ping-pong cache. The fast median filtering algorithm is used for image preprocessing, and finally the preprocessed image data is displayed on CRT. Experiments indicate that the design meets requirements of image sample quality and balances the real-time demand.
2014 ◽
Vol 912-914
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pp. 1222-1227
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Keyword(s):
2013 ◽
Vol 333-335
◽
pp. 980-983
Keyword(s):
1994 ◽
Vol 52
◽
pp. 218-219
Keyword(s):
Keyword(s):
2010 ◽
Vol 39
◽
pp. 523-528
Keyword(s):
2014 ◽
Vol 513-517
◽
pp. 1055-1058
Keyword(s):
2013 ◽
Vol 325-326
◽
pp. 1571-1575
Keyword(s):
2014 ◽
Vol 668-669
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pp. 836-839
Keyword(s):
2021 ◽
Vol 2074
(1)
◽
pp. 012004
Keyword(s):
2011 ◽
Vol 219-220
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pp. 170-173
Keyword(s):