Integrating Drain Gating and Lector Techniques for Leakage Power Reduction in Ultra Deep Submicron Technology

2021 5th International Conference on Trends in Electronics and Informatics (ICOEI) ◽

10.1109/icoei51242.2021.9453074 ◽

2021 ◽

Author(s):

Thokala Harikrishna ◽

Sanchita ◽

Shivam Kumar ◽

Amit Jain

Keyword(s):

Deep Submicron ◽

Power Reduction ◽

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Leakage Power Reduction in Deep Submicron VLSI Circuits Using Delay-Based Power Gating

National Academy Science Letters ◽

10.1007/s40009-019-00848-4 ◽

2019 ◽

Vol 43 (3) ◽

pp. 229-232 ◽

Author(s):

T. Thamaraimanalan ◽

P. Sampath

Keyword(s):

Deep Submicron ◽

Power Reduction ◽

Leakage Power ◽

Vlsi Circuits ◽

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An Overview of Various Leakage Power Reduction Techniques in Deep Submicron Technologies

2015 International Conference on Computing Communication Control and Automation ◽

10.1109/iccubea.2015.196 ◽

2015 ◽

Author(s):

Varsha Bendre ◽

A.K. Kureshi

Keyword(s):

Deep Submicron ◽

Power Reduction ◽

Leakage Power ◽

Reduction Techniques

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Combined subthreshold and gate-oxide leakage power reduction in deep-submicron CMOS Circuits

International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04. ◽

10.1109/iceec.2004.1374524 ◽

2005 ◽

Author(s):

R.S. Guindi

Keyword(s):

Deep Submicron ◽

Power Reduction ◽

Leakage Power ◽

Cmos Circuits ◽

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A novel approach for leakage power reduction in deep submicron technologies in CMOS VLSI circuits

2015 International Conference on Computer, Communication and Control (IC4) ◽

10.1109/ic4.2015.7375536 ◽

2015 ◽

Author(s):

Ajay Kumar Dadoria ◽

Kavita Khare ◽

R. P. Singh

Keyword(s):

Deep Submicron ◽

Power Reduction ◽

Leakage Power ◽

Vlsi Circuits ◽

Novel Approach ◽

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Critical path delay and leakage power reduction during test in deep submicron IC's

2012 International Conference on Emerging Trends in Science, Engineering and Technology (INCOSET) ◽

10.1109/incoset.2012.6513924 ◽

2012 ◽

Author(s):

P. PattunnaRajam ◽

Reebakorah

Keyword(s):

Critical Path ◽

Deep Submicron ◽

Power Reduction ◽

Leakage Power ◽

Critical Path Delay

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Leakage Power Reduction Techniques in Deep Submicron Technologies for VLSI Applications

Procedia Engineering ◽

10.1016/j.proeng.2012.01.976 ◽

2012 ◽

Vol 30 ◽

pp. 1163-1170 ◽

Author(s):

M.Geetha Priya ◽

K. Baskaran ◽

D. Krishnaveni

Keyword(s):

Deep Submicron ◽

Power Reduction ◽

Leakage Power ◽

Reduction Techniques

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An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors

Advances in Computer Systems Architecture - Lecture Notes in Computer Science ◽

10.1007/11859802_62 ◽

2006 ◽

pp. 588-594 ◽

Author(s):

Chengyi Zhang ◽

Hongwei Zhou ◽

Minxuan Zhang ◽

Zuocheng Xing

Keyword(s):

Reduction Method ◽

Deep Submicron ◽

Power Reduction ◽

Leakage Power ◽

Instruction Cache

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A Review on Various Leakage Power Reduction Techniques in Deep Submicron Technologies in CMOS VLSI Circuits

International Journal of Energy Technology and Management ◽

10.21742/ijetm.2017.1.2.03 ◽

2017 ◽

Vol 1 (2) ◽

pp. 17-22

Author(s):

Aloka Tamta ◽

◽

Rachna Arya ◽

Keyword(s):

Deep Submicron ◽

Power Reduction ◽

Leakage Power ◽

Vlsi Circuits ◽

Reduction Techniques ◽

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LEAKAGE POWER REDUCTION USING MULTI MODAL DRIVEN HIERARCHICAL POWER MODE SWITCHES

i-manager s Journal on Circuits and Systems ◽

10.26634/jcir.6.2.14291 ◽

2018 ◽

Vol 6 (2) ◽

pp. 1

Author(s):

SEKHAR REDDY M. CHANDRA ◽

REDDY P. RAMANA ◽

◽

Keyword(s):

Power Reduction ◽

Leakage Power ◽

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Effect of leakage power reduction techniques on combinational circuits

2015 Online International Conference on Green Engineering and Technologies (IC-GET) ◽

10.1109/get.2015.7453862 ◽

2015 ◽

Author(s):

M. Manoranjani ◽

T. Ravi ◽

R. Ramya

Keyword(s):

Power Reduction ◽

Leakage Power ◽

Combinational Circuits ◽

Reduction Techniques

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