Combined subthreshold and gate-oxide leakage power reduction in deep-submicron CMOS Circuits
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2019 ◽
Vol 43
(3)
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pp. 229-232
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2008 ◽
Vol 48
(11-12)
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pp. 1786-1790
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2014 ◽
Vol 2
(4)
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pp. 133-136
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