High Performance Design and Implementation of Nemesis Communication Layer for Two-Sided and One-Sided MPI Semantics in MVAPICH2

2010 ◽  
Author(s):  
Miao Luo ◽  
Sreeram Potluri ◽  
Ping Lai ◽  
Emilio P. Mancini ◽  
Hari Subramoni ◽  
...  
Keyword(s):  
High Performance ◽  
Design And Implementation ◽  
Communication Layer ◽  
High Performance Design

A High Performance Design and Implementation of the Virtual Interface Architecture

2003 ◽  
pp. 125-135
Author(s):  
Yu Chen ◽  
Zhenqiang Jiao ◽  
Jun Xie ◽  
Zhihui Du ◽  
Peng Liu ◽  
...  
Keyword(s):  
High Performance ◽  
Virtual Interface ◽  
Design And Implementation ◽  
High Performance Design

Design and implementation of high performance array multipliers for digital circuits

2013 ◽  
Author(s):  
P. Srivastava ◽  
V. Vishant ◽  
R. K. Singh ◽  
R. K. Nagaria
Keyword(s):  
High Performance ◽  
Digital Circuits ◽  
Design And Implementation ◽  
Array Multipliers

Design and implementation of a high performance network security processor

2010 ◽  
Vol 97 (3) ◽  
pp. 309-325 ◽  
Author(s):  
Haixin Wang ◽  
Guoqiang Bai ◽  
Hongyi Chen
Keyword(s):  
Network Security ◽  
High Performance ◽  
Design And Implementation ◽  
Network Security Processor ◽  
Security Processor

Design and implementation of real-time rowing simulator (ReTRoS) for high-performance and low-injury — A preliminary work

2016 ◽  
Author(s):  
Muhammad Syafoan Safiee ◽  
Afandi Ahmad ◽  
Zarina Tukiran ◽  
Muhammad Faris Roslan ◽  
Muhammad Muzakkir Mohd Nadzri
Keyword(s):  
Real Time ◽  
High Performance ◽  
Design And Implementation ◽  
Preliminary Work

High Performance Design for Redis with Fast Event-Driven RDMA RPCs

2020 ◽  
pp. 195-210
Author(s):  
Xuecheng Qi ◽  
Huiqi Hu ◽  
Xing Wei ◽  
Chengcheng Huang ◽  
Xuan Zhou ◽  
...  
Keyword(s):  
High Performance ◽  
Event Driven ◽  
High Performance Design

scholarly journals Design and implementation of CNTFET based ternary 1x1 memories

2019 ◽  
Vol 8 (3) ◽  
pp. 175 ◽  
Author(s):  
S.Tamil Selvan ◽  
M. Sundararajan
Keyword(s):  
High Performance ◽  
Data Access ◽  
Cmos Technology ◽  
Access Time ◽  
The Novel ◽  
Design And Implementation ◽  
Technology Process ◽  
Sram Cell ◽  
And Performance ◽  
Power Application

In this paper presented Design and implementation of CNTFET based Ternary 1x1 RAM memories high-performance digital circuits. CNTFET Ternary 1x1 SRAM memories is implement using 32nm technology process. The CNTFET decresase the diameter and performance matrics like delay,power and power delay, The CNTFET Ternary 6T SRAM cell consists of two cross coupled Ternary inverters one is READ and another WRITE operations of the Ternary 6T SRAM cell are performed with the Tritline using HSPICE and Tanner tools in this tool is performed high accuracy. The novel based work can be used for Low Power Application and Access time is less of compared to the conventional CMOS Technology. The CNTFET Ternary 6T SRAM array module (1X1) in 32nm technology consumes only 0.412mW power and data access time is about 5.23ns.

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