Design and implementation of dynamic key based stream cipher for cryptographic processor

2015 ◽  
Author(s):  
K.K. Soundra Pandian ◽  
Saptadeep Pal ◽  
Kailash Chandra Ray
Keyword(s):  
Stream Cipher ◽  
Design And Implementation ◽  
Dynamic Key

scholarly journals Design and Implementation of LCG-Trivium Key Stream Generator into FPGA

2018 ◽  
Vol 7 (3) ◽  
pp. 186
Author(s):  
Tchahou Tchendjeu A. E ◽  
Tchitnga Robert ◽  
Fotsin Hilaire B
Keyword(s):  
Stream Cipher ◽  
Clock Cycle ◽  
State Machine ◽  
Initial Value ◽  
Design And Implementation ◽  
Generator Circuit ◽  
Quartus Ii ◽  
Initialization Vector ◽  
Linear Congruential Generator ◽  
Linear Congruential

<p>This paper presents the Design and implementation into Field ProgrammableGate Array (FPGA) of a combine stream cipher and a simple linear congruential generator circuit to produce key stream. The LCG circuit is used to produce initialization vector (IV) each 2<sup>64</sup> clock cycle to the cipher trivium in other to strengthen the complexity of the cipher to known attacks on trivium. The LCGTrivium is designed to generate 2<sup>144</sup> bits of keystream from an 80-bits secret and a variable 80-bits initial value. To implement the LCG-Trivium on FPGA, we use VHDL to build a simple LCG and Trivium and a state machine to synchronize the functioning of the LCG and Trivium. The number of gates, memory and speed requirement on FPGA is giving after analysis. The design is simulated, synthesized and implemented in Quartus II 10.1, ModelSim-Altera 6.5 and Cyclone IV E EP4CE115F29C7N.</p>

The Design and Implementation of a Heterogeneous Multi-Core Security Chip Architecture Based on Shared Memory System

2014 ◽  
Vol 668-669 ◽  
pp. 1314-1318
Author(s):  
Lei Zhang ◽  
Ren Ping Dong ◽  
Chang Zhang ◽  
Ya Ping Yu
Keyword(s):  
Low Power ◽  
Computer Architecture ◽  
Shared Memory ◽  
High Performance ◽  
Stream Cipher ◽  
Ic Card ◽  
Task Partitioning ◽  
Core System ◽  
Design And Implementation ◽  
Encryption And Decryption

With the existence of traditional SOC chip, the encryption and decryption speed and low power cannot meet the computing needs of the modern diversity, then we present a heterogeneous multi-core system which designed based on shared memory on the Xilinx Virtex-5 platform. This paper is in-depth research about heterogeneous multi-core password architecture, static task partitioning, scheduling strategy and the communication mechanism between cores. The three cores systems are designed and builded based on shared memory to realize ZUC algorithm which generates a stream cipher on virtex-5 platform. The three microblaze cores are responsible for inter-core communication, the implementation of ZUC algorithm and articulating IC card to read keys. Through the design of three cores system, give full play to the hardware, software and computer architecture parallelism at all levels to improve the performance of the algorithm to achieve high performance green computing.

scholarly journals Design and Implementation of Stream Cipher Using Neural Network

2009 ◽  
Vol 6 (1) ◽  
pp. 237-249
Author(s):  
Siddeq Ameen ◽  
Mazin Othman ◽  
Safwan Hasoon ◽  
Moyed Al-Razaq
Keyword(s):  
Neural Network ◽  
Stream Cipher ◽  
Design And Implementation

Reconfigurable Design and Implementation of Data Extraction and Permutation Facing Stream Cipher Algorithm

2011 ◽  
Vol 130-134 ◽  
pp. 2903-2906
Author(s):  
Fei Gao ◽  
Zi Bin Dai
Keyword(s):  
Stream Cipher ◽  
Data Extraction ◽  
Data Distribution ◽  
Design And Implementation ◽  
Control Information ◽  
Reconfigurable Design ◽  
Butterfly Network ◽  
Information Generation ◽  
Crossbar Network ◽  
Nonlinear Transformation Unit

For design of a class of stream cipher algorithm reconfigurable coprocessor, it is necessary to realize efficient and flexible distribution between the initial chaos source generator and nonlinear transformation unit. From the analysis, it can be seen that the data distribution should have any data extraction and repeatable permutation characteristics. In this paper, design of data distribution network’s main circuit based on Inverse Butterfly network and Crossbar network is presented. And an algorithm of control information generation is given. By analysis and comparison with other realization ways, this design can save 16% hardware resources.

scholarly journals Design and Implementation of LCG-Trivium Key Stream Generator into FPGA

2018 ◽  
Vol 7 (3) ◽  
pp. 180
Author(s):  
Tchahou Tchendjeu A. E ◽  
Tchitnga Robert ◽  
Fotsin Hilaire B
Keyword(s):  
Stream Cipher ◽  
Clock Cycle ◽  
State Machine ◽  
Initial Value ◽  
Design And Implementation ◽  
Generator Circuit ◽  
Quartus Ii ◽  
Initialization Vector ◽  
Linear Congruential Generator ◽  
Linear Congruential

<p>This paper presents the Design and implementation into Field ProgrammableGate Array (FPGA) of a combine stream cipher and a simple linear congruential generator circuit to produce key stream. The LCG circuit is used to produce initialization vector (IV) each 2<sup>64</sup> clock cycle to the cipher trivium in other to strengthen the complexity of the cipher to known attacks on trivium. The LCGTrivium is designed to generate 2<sup>144</sup> bits of keystream from an 80-bits secret and a variable 80-bits initial value. To implement the LCG-Trivium on FPGA, we use VHDL to build a simple LCG and Trivium and a state machine to synchronize the functioning of the LCG and Trivium. The number of gates, memory and speed requirement on FPGA is giving after analysis. The design is simulated, synthesized and implemented in Quartus II 10.1, ModelSim-Altera 6.5 and Cyclone IV E EP4CE115F29C7N.</p>

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