scholarly journals Design and Implementation of LCG-Trivium Key Stream Generator into FPGA

2018 ◽  
Vol 7 (3) ◽  
pp. 186
Author(s):  
Tchahou Tchendjeu A. E ◽  
Tchitnga Robert ◽  
Fotsin Hilaire B
Keyword(s):  
Stream Cipher ◽  
Clock Cycle ◽  
State Machine ◽  
Initial Value ◽  
Design And Implementation ◽  
Generator Circuit ◽  
Quartus Ii ◽  
Initialization Vector ◽  
Linear Congruential Generator ◽  
Linear Congruential

<p>This paper presents the Design and implementation into Field ProgrammableGate Array (FPGA) of a combine stream cipher and a simple linear congruential generator circuit to produce key stream. The LCG circuit is used to produce initialization vector (IV) each 2<sup>64</sup> clock cycle to the cipher trivium in other to strengthen the complexity of the cipher to known attacks on trivium. The LCGTrivium is designed to generate 2<sup>144</sup> bits of keystream from an 80-bits secret and a variable 80-bits initial value. To implement the LCG-Trivium on FPGA, we use VHDL to build a simple LCG and Trivium and a state machine to synchronize the functioning of the LCG and Trivium. The number of gates, memory and speed requirement on FPGA is giving after analysis. The design is simulated, synthesized and implemented in Quartus II 10.1, ModelSim-Altera 6.5 and Cyclone IV E EP4CE115F29C7N.</p>

scholarly journals Design and Implementation of LCG-Trivium Key Stream Generator into FPGA

2018 ◽  
Vol 7 (3) ◽  
pp. 180
Author(s):  
Tchahou Tchendjeu A. E ◽  
Tchitnga Robert ◽  
Fotsin Hilaire B
Keyword(s):  
Stream Cipher ◽  
Clock Cycle ◽  
State Machine ◽  
Initial Value ◽  
Design And Implementation ◽  
Generator Circuit ◽  
Quartus Ii ◽  
Initialization Vector ◽  
Linear Congruential Generator ◽  
Linear Congruential

<p>This paper presents the Design and implementation into Field ProgrammableGate Array (FPGA) of a combine stream cipher and a simple linear congruential generator circuit to produce key stream. The LCG circuit is used to produce initialization vector (IV) each 2<sup>64</sup> clock cycle to the cipher trivium in other to strengthen the complexity of the cipher to known attacks on trivium. The LCGTrivium is designed to generate 2<sup>144</sup> bits of keystream from an 80-bits secret and a variable 80-bits initial value. To implement the LCG-Trivium on FPGA, we use VHDL to build a simple LCG and Trivium and a state machine to synchronize the functioning of the LCG and Trivium. The number of gates, memory and speed requirement on FPGA is giving after analysis. The design is simulated, synthesized and implemented in Quartus II 10.1, ModelSim-Altera 6.5 and Cyclone IV E EP4CE115F29C7N.</p>

scholarly journals A Technique for Securing Multiple Digital Images Based on 2D Linear Congruential Generator, Silver Ratio, and Galois Field

IEEE Access ◽  
2021 ◽  
pp. 1-1
Author(s):  
Abdul Gaffar ◽  
Anand B. Joshi ◽  
Sonali Singh ◽  
Vishnu Narayan Mishra ◽  
Hamurabi Gamboa Rosales ◽  
...  
Keyword(s):  
Digital Images ◽  
Galois Field ◽  
Congruential Generator ◽  
Linear Congruential Generator ◽  
Linear Congruential

scholarly journals Co-simulation of linear congruential generator by using Xilinx system generator and MATLAB Simulink

2021 ◽  
Vol 10 (2) ◽  
pp. 109
Author(s):  
Suneeta Suneeta
Keyword(s):  
Circuit Simulation ◽  
Prime Numbers ◽  
Matlab Simulink ◽  
System Generator ◽  
Congruential Generator ◽  
Wide Range ◽  
Linear Congruential Generator ◽  
Full Period ◽  
Xilinx System Generator ◽  
Linear Congruential

<p>Arbitrary numerals are utilized in a wide range of uses. Genuine arbitrary numeral generators are moderate and costly for some applications while pseudo arbitrary numeral generators (RNG) do the trick for most applications. This paper fundamentally concentrates around the co-simulation of the linear congruential generator (LCG) model utilizing the Xilinx System generator and checking on Matlab Simulink. The design is obtained from the LCG calculation offered by Lehmer. Word lengths decrease strategy has been utilized to streamline the circuit. Simulation has been done effectively. The effective N bit LCG is structured and tried by utilizing demonstrating in MatLab Simulink. The Co-simulation of the model is done by utilizing the Xilinx system generator. This paper conducts an exhaustive search for the best arbitrary numeral generator in a full period linear congruential generator (LCG) with the largest prime numbers.</p>

scholarly journals Implementasi Linear Congruential Generator Dalam Rancang Bangun Aplikasi Game Peduli Lingkungan

2013 ◽  
Vol 2 (1) ◽  
pp. 85
Author(s):  
I Putu Gede Budayasa ◽  
Gusde Paryatna
Keyword(s):  
Visual Basic ◽  
Congruential Generator ◽  
Linear Congruential Generator ◽  
Linear Congruential ◽  
Visual Basic 6.0

Hal yang merugikan lingkungan banyak terjadi sehingga diperlukan kesadaran dari setiap orang agar lebih peduli terhadap lingkungan. Dengan demikian maka  dampak buruk akibat kondisi lingkungan yang kurang baik dapat dikurangi hingga tidak  ada lagi dampak buruk tersebut ke depannya. Menumbuhkan kepedulian terhadap lingkungan harus dimulai sejak usia anak-anak.  Game untuk mengajarkan kepedulian terhadap lingkungan merupakan sebuah permainan yang membuat pemain yang memainkan selalu ingat untuk menjaga lingkungan tetap dalam keadaan baik. Pemainnya diarahkan untuk selalu melakukan hal-hal yang berdampak positif bagi lingkungan terutama dalam kebersihan dan pencegahan terhadap bencana seperti banjir. Tujuan dirancangnya aplikasi game ini adalah untuk memberikan pengetahuan bagaimana menjaga lingkungan agar tetap dalam keadaan baik terutama bagi anak-anak dan menjadikan kebiasaan di kalangan anak-anak untuk tidak melakukan hal yang merugikan lingkungan sehingga terbawa hingga dewasa. Nantinya aplikasi game ini dapat digunakan sebagai media pembelajaran bagi anak-anak.Rancang bangun game ini menggunakan Microsoft Visual Basic 6.0. Aplikasi ini tidak membutuhkan spesifikasi komputer yang tinggi sehingga mudah digunakan. Metode pembangkit bilangan acak yang diterapkan adalah linear congruential generator (LCG) untuk salah satu proses yang ada di dalam game. Tampilan dari game  ini dibuat menarik dengan pemilihan warna yang sesuai dengan karakter anak-anak yang ceria. Dalam aplikasinya game ini diberi nama “Lingkunganku”.

scholarly journals Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA

Sensors ◽  
2020 ◽  
Vol 20 (23) ◽  
pp. 6909
Author(s):  
Francisco Eugenio Potestad-Ordóñez ◽  
Manuel Valencia-Barrero ◽  
Carmen Baena-Oliva ◽  
Pilar Parra-Fernández ◽  
Carlos Jesús Jiménez-Fernández
Keyword(s):  
Stream Cipher ◽  
Internal State ◽  
Clock Cycle ◽  
Fault Analysis ◽  
Invasive Technique ◽  
Sensitive Information ◽  
Secret Key ◽  
Key Recovery ◽  
Differential Fault Analysis ◽  
Secret Keys

One of the best methods to improve the security of cryptographic systems used to exchange sensitive information is to attack them to find their vulnerabilities and to strengthen them in subsequent designs. Trivium stream cipher is one of the lightweight ciphers designed for security applications in the Internet of things (IoT). In this paper, we present a complete setup to attack ASIC implementations of Trivium which allows recovering the secret keys using the active non-invasive technique attack of clock manipulation, combined with Differential Fault Analysis (DFA) cryptanalysis. The attack system is able to inject effective transient faults into the Trivium in a clock cycle and sample the faulty output. Then, the internal state of the Trivium is recovered using the DFA cryptanalysis through the comparison between the correct and the faulty outputs. Finally, a backward version of Trivium was also designed to go back and get the secret keys from the initial internal states. The key recovery has been verified with numerous simulations data attacks and used with the experimental data obtained from the Application Specific Integrated Circuit (ASIC) Trivium. The secret key of the Trivium were recovered experimentally in 100% of the attempts, considering a real scenario and minimum assumptions.

Design and Implementation of Intelligent Digital Photo Frame Based on FPGA

2013 ◽  
Vol 380-384 ◽  
pp. 3296-3299
Author(s):  
Dan Dan Han ◽  
Tian Chi Zhang ◽  
Jing Zhang
Keyword(s):  
System Optimization ◽  
Software System ◽  
Digital Photo ◽  
Design And Implementation ◽  
Traditional Design ◽  
Quartus Ii ◽  
Functional Correctness ◽  
Integrate Design ◽  
High Degree ◽  
Observation Results

SOPC technology of Nios II is Used for the design of intelligent digital photo frame in this paper. Developers can integrate design according to actual needs, fundamentally changing the lack of traditional design. Digital photo frame as a whole project is divided into two parts of the hardware module and software system. Functional correctness is verified by Quartus II, further downloaded to the FPGA for debugging, the observation results showed that digital photo frame has a high degree of freedom in the system optimization, which can be extended the life of the product on the market, greatly improving the performance of multi-function digital photo frame.

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