A Novel Process Variation Model for Test Cost Reduction in Wafers with Addressable Monitoring Structures

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict49897.2020.9278230 ◽

2020 ◽

Author(s):

Gui-Feng Ren ◽

Zheng Shi

Keyword(s):

Cost Reduction ◽

Process Variation ◽

Test Cost ◽

Test Cost Reduction ◽

Variation Model

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Wafer-level process variation-driven probe-test flow selection for test cost reduction in analog/RF ICs

2016 IEEE 34th VLSI Test Symposium (VTS) ◽

10.1109/vts.2016.7477263 ◽

2016 ◽

Author(s):

Ali Ahmadi ◽

Amit Nahar ◽

Bob Orr ◽

Michael Past ◽

Yiorgos Makris

Keyword(s):

Cost Reduction ◽

Process Variation ◽

Wafer Level ◽

Test Cost ◽

Test Cost Reduction ◽

Test Flow ◽

Selection For ◽

Level Process ◽

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Reduced-Pin-Count BOST for Test-Cost Reduction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2021.3065912 ◽

2021 ◽

pp. 1-1

Author(s):

Youngkwang Lee ◽

Young-woo Lee ◽

Sungyoul Seo ◽

Sungho Kang

Keyword(s):

Cost Reduction ◽

Test Cost ◽

Test Cost Reduction

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Black-Box Test-Cost Reduction Based on Bayesian Network Models

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2020.2994257 ◽

2020 ◽

pp. 1-1

Author(s):

Renjian Pan ◽

Zhaobo Zhang ◽

Xin Li ◽

Krishnendu Chakrabarty ◽

Xinli Gu

Keyword(s):

Bayesian Network ◽

Cost Reduction ◽

Network Models ◽

Black Box ◽

Test Cost ◽

Test Cost Reduction ◽

Bayesian Network Models

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Reliable test architecture with test cost reduction for systolic based DNN accelerators

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2021.3108415 ◽

2021 ◽

pp. 1-1

Author(s):

Muhammad Ibtesam ◽

Umair Saeed Solangi ◽

Jinuk Kim ◽

Muhammad Adil Ansari ◽

Sungju Park

Keyword(s):

Cost Reduction ◽

Test Cost ◽

Reliable Test ◽

Test Cost Reduction ◽

Test Architecture

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A scan disabling-based BAST scheme for test cost reduction

IEICE Electronics Express ◽

10.1587/elex.8.1367 ◽

2011 ◽

Vol 8 (16) ◽

pp. 1367-1373 ◽

Author(s):

Zhiqiang You ◽

Weizheng Wang ◽

Zhiping Dou ◽

Peng Liu ◽

Jishun Kuang

Keyword(s):

Cost Reduction ◽

Test Cost ◽

Test Cost Reduction

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BIST-aided scan test - a new method for test cost reduction

Proceedings. 21st VLSI Test Symposium, 2003. ◽

10.1109/vtest.2003.1197675 ◽

2003 ◽

Author(s):

T. Hiraide ◽

Kwame Osei Boateng ◽

H. Konishi ◽

K. Itaya ◽

M. Emori ◽

...

Keyword(s):

Cost Reduction ◽

Test Cost ◽

Scan Test ◽

Test Cost Reduction

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Innovative practices session 3C: Industrial practices of test cost reduction techniques: Impact and design tradeoffs

2010 28th VLSI Test Symposium (VTS) ◽

10.1109/vts.2010.5469600 ◽

2010 ◽

Author(s):

Sarveswara Tammali

Keyword(s):

Cost Reduction ◽

Test Cost ◽

Reduction Techniques ◽

Test Cost Reduction ◽

Design Tradeoffs

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Yield improvement and test cost reduction for TSV based 3D stacked ICs

2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) ◽

10.1109/dtis.2011.5941404 ◽

2011 ◽

Author(s):

Said Hamdioui

Keyword(s):

Cost Reduction ◽

Yield Improvement ◽

Test Cost ◽

Test Cost Reduction

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Segmented scan architecture using segment grouping for test cost reduction

2008 International SoC Design Conference ◽

10.1109/socdc.2008.4815651 ◽

2008 ◽

Author(s):

Myung-Hoon Yang ◽

Taejin Kim ◽

Yongjoon Kim ◽

Sungho Kang

Keyword(s):

Cost Reduction ◽

Test Cost ◽

Test Cost Reduction

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The test cost reduction benefits of combining a hierarchical DFT methodology with EDT channel sharing — A case study

2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) ◽

10.1109/dtis.2018.8368556 ◽

2018 ◽

Author(s):

Binghua Lu ◽

Selina Sha ◽

Jincheng Wang ◽

Zhigao Zhang ◽

Fanjin Meng ◽

...

Keyword(s):

Cost Reduction ◽

Test Cost ◽

Test Cost Reduction

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