Genetic algorithms for scan path design

Proceedings of 9th International Conference on VLSI Design ◽

10.1109/icvd.1996.489469 ◽

2002 ◽

Author(s):

C.P. Ravikumar ◽

N. Rajarajan

Keyword(s):

Genetic Algorithms ◽

Path Design ◽

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The Economics of Scan-Path Design for Testability

Economics of Electronic Design, Manufacture and Test ◽

10.1007/978-1-4757-5048-5_5 ◽

1994 ◽

pp. 53-67 ◽

Author(s):

Prab Varma ◽

Tushar Gheewala

Keyword(s):

Design For Testability ◽

Path Design ◽

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Arrangement of latches in scan-path design to improve delay fault coverage

Proceedings. International Test Conference 1990 ◽

10.1109/test.1990.114046 ◽

2002 ◽

Author(s):

W. Mao ◽

M.D. Ciletti

Keyword(s):

Fault Coverage ◽

Delay Fault ◽

Path Design ◽

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Cost-free scan: a low-overhead scan path design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.720320 ◽

1998 ◽

Vol 17 (9) ◽

pp. 852-861 ◽

Author(s):

Chih-Chang Lin ◽

M. Marek-Sadowska ◽

M.T.-C. Lee ◽

Kuang-Chien Chen

Keyword(s):

Path Design ◽

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Reducing correlation to improve coverage of delay faults in scan-path design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.277638 ◽

1994 ◽

Vol 13 (5) ◽

pp. 638-646 ◽

Author(s):

Weiwei Mao ◽

M.D. Ciletti

Keyword(s):

Delay Faults ◽

Path Design ◽

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On scan path design for stuck-open and delay fault detection

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246553 ◽

2002 ◽

Author(s):

J. Leenstra ◽

M. Koch ◽

T. Schwederski

Keyword(s):

Fault Detection ◽

Delay Fault ◽

Path Design ◽

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Correlation-reduced scan-path design to improve delay fault coverage

Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91 ◽

10.1145/127601.127631 ◽

1991 ◽

Author(s):

Weiwei Mao ◽

Michael D. Ciletti

Keyword(s):

Fault Coverage ◽

Delay Fault ◽

Path Design ◽

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The economics of scan-path design for testability

Journal of Electronic Testing ◽

10.1007/bf00972078 ◽

1994 ◽

Vol 5 (2-3) ◽

pp. 179-193 ◽

Author(s):

Prab Varma ◽

Tushar Gheewala

Keyword(s):

Design For Testability ◽

Path Design ◽

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Cost-free scan: a low-overhead scan path design methodology

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ◽

10.1109/iccad.1995.480167 ◽

2002 ◽

Author(s):

Chih-Chang Lin ◽

M.T.-C. Lee ◽

M. Marek-Sadowska ◽

Kuang-Chien Chen

Keyword(s):

Design Methodology ◽

Path Design ◽

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An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis

2019 IEEE International Test Conference in Asia (ITC-Asia) ◽

10.1109/itc-asia.2019.00023 ◽

2019 ◽

Author(s):

Tsuyoshi Iwagaki ◽

Sho Yuasa ◽

Hideyuki Ichihara ◽

Tomoo Inoue

Keyword(s):

Logic Synthesis ◽

Empirical Approach ◽

Structural Interpretation ◽

Path Design ◽

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Hierarchical time-optimal control of a continuous copolymerization reactor during start-up or grade change operation using genetic algorithms

Computers & Chemical Engineering ◽

10.1016/s0098-1354(97)00186-5 ◽

1997 ◽

Vol 21 (1-2) ◽

pp. S1037-S1042

Author(s):

H Moo

Keyword(s):

Optimal Control ◽

Genetic Algorithms ◽

Time Optimal Control ◽

Grade Change ◽

Start Up ◽

Time Optimal ◽

Change Operation ◽

Grade Change Operation

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