Experimental technology and characterization of self-aligned 0.1µm-gate-length low-temperature operation NMOS devices

Author(s):  
G.A. Sai-Halasz ◽  
M.R. Wordeman ◽  
D.P. Kern ◽  
E. Ganin ◽  
S. Rishton ◽  
...  
1987 ◽  
Vol 8 (10) ◽  
pp. 463-466 ◽  
Author(s):  
G.A. Sai-Halasz ◽  
M.R. Wordeman ◽  
D.P. Kern ◽  
E. Ganin ◽  
S. Rishton ◽  
...  

2011 ◽  
Vol 324 ◽  
pp. 407-410 ◽  
Author(s):  
Jalal Jomaah ◽  
Majida Fadlallah ◽  
Gerard Ghibaudo

A review of recent results concerning the DC characterization of FD- and Double Gate SOI MOSFET’s and FinFETs in modern CMOS technologies is given. By proper extraction techniques, distinction between the different interaction mechanisms is done. Parameter extraction conducted at room and low temperature clearly indicates that the mobility is directly impacted by shrinking the gate length in sub 100nm architectures.


2017 ◽  
Vol 834 ◽  
pp. 012001
Author(s):  
R. Laviéville ◽  
C. Le Royer ◽  
S. Barraud ◽  
G. Ghibaudo

2015 ◽  
Vol 135 (7) ◽  
pp. 733-738 ◽  
Author(s):  
Yasushi Kobayashi ◽  
Yoshihiro Nakata ◽  
Tomoji Nakamura ◽  
Mayumi B. Takeyama ◽  
Masaru Sato ◽  
...  
Keyword(s):  

2017 ◽  
Vol 122 (8) ◽  
pp. 084103 ◽  
Author(s):  
E. Smirnova ◽  
A. Sotnikov ◽  
S. Ktitorov ◽  
H. Schmidt

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