To improve the shortcomings of long arbitration–allocation time and large power consumption in conventional network on chips, this paper proposes a high speed multi-resource arbiter with active virtual channel allocation. Through arbitrating the acknowledgement signals of virtual channels, the virtual channels can attend the arbitration–allocation process actively. Thus reduces the virtual channel allocation time. Furthermore, the proposed multi-resource arbiter has integrated the function of virtual channel allocation, which improves the performance and simplifies the design process simultaneously. Null convention logic units are used to make the circuit quasi-delay insensitive and high robustness. The proposed multi-resource arbiter is implemented based on SMIC 0.18 μm standard CMOS technology. Results have shown that the arbitration–allocation time of the arbiter is only 824.1 ps, which reduced 25.1% compared with the conventional one. The power consumption and the area are slightly larger than the conventional ones. The proposed high speed multi-resource arbiter is suitable for high performance and high robustness interconnections of on chip networks.
A High-throughput Router Architecture with On-the-fly Virtual Channel Allocation for On-chip Networks
