Defect analysis, test generation and fault simulation for gate oxide shorts in CMOS ICs

Mapping Intimacies ◽

10.1109/iscas.1990.112567 ◽

2002 ◽

Author(s):

S.I. Syed ◽

D.M. Wu

Keyword(s):

Test Generation ◽

Fault Simulation ◽

Defect Analysis

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Defect analysis and test generation for gate oxide shorts in CMOS ICs

10.1109/cicc.1990.124823 ◽

2002 ◽

Author(s):

S.I. Syed ◽

D.M. Wu

Keyword(s):

Test Generation ◽

Defect Analysis

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Test generation for gate oxide short in CMOS ICs

10.1109/secon.1990.117983 ◽

2002 ◽

Author(s):

S.I. Syed ◽

D.M. Wu

Keyword(s):

Test Generation ◽

Gate Oxide Short

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Functional Test Generation For finite State Machines With Concurrent Fault Simulation

10.1109/atw.1994.747832 ◽

2005 ◽

Author(s):

N.L. Cooray ◽

E.W. Czeck

Keyword(s):

Test Generation ◽

Fault Simulation ◽

Finite State Machines ◽

Functional Test ◽

State Machines ◽

Finite State ◽

Concurrent Fault Simulation

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Fault simulation and test generation

Electronic Design Automation ◽

10.1016/b978-0-12-374364-0.50021-7 ◽

2009 ◽

pp. 851-917

Author(s):

James C.-M. Li ◽

Michael S. Hsiao

Keyword(s):

Test Generation ◽

Fault Simulation

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Behavioral test generation/fault simulation

IEEE Potentials ◽

10.1109/mp.2003.1180938 ◽

2003 ◽

Vol 22 (1) ◽

pp. 27-32 ◽

Author(s):

Chien-In Henry Chen

Keyword(s):

Test Generation ◽

Fault Simulation ◽

Behavioral Test

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A delay fault model for at-speed fault simulation and test generation

2006 IEEE/ACM International Conference on Computer Aided Design ◽

10.1145/1233501.1233521 ◽

2006 ◽

Author(s):

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Test Generation ◽

Fault Simulation ◽

Fault Model ◽

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Performance trade-offs in a parallel test generation/fault simulation environment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.103504 ◽

1991 ◽

Vol 10 (12) ◽

pp. 1542-1558 ◽

Author(s):

S. Patil ◽

P. Banerjee

Keyword(s):

Test Generation ◽

Fault Simulation ◽

Simulation Environment ◽

Parallel Test ◽

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System level test generation and fault simulation for VLSI circuits

10.1109/icasic.1996.562836 ◽

2002 ◽

Author(s):

Yuhai Ma ◽

Yihe Sun ◽

Hongyi Chen

Keyword(s):

Test Generation ◽

Fault Simulation ◽

Vlsi Circuits ◽

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EDIF: test generation and fault simulation

Digest of Papers. COMPCON Spring 88 Thirty-Third IEEE Computer Society International Conference ◽

10.1109/cmpcon.1988.4887 ◽

1988 ◽

Author(s):

J.P. Eurich

Keyword(s):

Test Generation ◽

Fault Simulation

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Gate Oxide Defect Analysis Using Scanning Electron Microscopy (SEM)/Metal Oxide Semiconductor (MOS)/Electron Beam Induced Current (EBIC) with Sub-Nano Ampere Current Breakdown

Solid State Phenomena ◽

10.4028/www.scientific.net/ssp.63-64.395 ◽

1998 ◽

Vol 63-64 ◽

pp. 395-406 ◽

Author(s):

M. Tamatsuka ◽

K. Miki

Keyword(s):

Electron Microscopy ◽

Scanning Electron Microscopy ◽

Electron Beam ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Induced Current ◽

Defect Analysis ◽

Electron Beam Induced Current ◽

Scanning Electron

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