Testing for gate oxide short defects using the detectability interval paradigm

This paper addresses the detection improvement of Gate Oxide Short defect using a delay test strategy. To achieve this objective, the concept of detectability interval is first introduced in the context of detection of short defects using Boolean test technique. Then this paradigm is extended to the detection of Gate Oxide Short defects using delay testing. Finally, it is shown that it is possible to significantly improve the detection of this kind of defect.

Floating Substrate Passive Voltage Contrast (FSPVC)

Light emission [1,2] and passive voltage contrast (PVC) [3,4] are common failure analysis tools that can quickly identify and localize gate oxide short sites. In the past, PVC was not used on electrically floating substrates or SOI (silicon-on-insulator) devices due to the conductive path needed to “bleed off” charge. In PVC, the SEM’s primary beam induces different equilibrium potentials on floating versus grounded (0 V) conductors, thus generating different secondary electron emission intensities for fault localization. Recently we obtained PVC signals on bulk silicon floating substrates and SOI devices. In this paper, we present details on identifying and validating gate shorts utilizing this Floating Substrate PVC (FSPVC) method.