Domino free 4-path time-interleaved second order sigma-delta modulator

Author(s):  
Kye-Shin Lee ◽  
Yunyoung Choi ◽  
F. Maloberti
2005 ◽  
Vol 43 (3) ◽  
pp. 225-235 ◽  
Author(s):  
Kye-shin Lee ◽  
Yunyoung Choi ◽  
Franco Maloberti

2004 ◽  
Vol 1 (3) ◽  
pp. 37-44 ◽  
Author(s):  
Dragisa Milovanovic ◽  
Milan Savic ◽  
Miljan Nikolic

As a part of wider project sigma-delta modulator was designed. It represents an A/D part of a power meter IC. Requirements imposed were: SNDR and dynamic range > 50 dB for maximum input swing of 250 mV differential at 50 Hz. Over sampling ratio is 128 with clock frequency of 524288 Hz which gives bandwidth of 2048 Hz. Circuit is designed in 3.3 V supply standard CMOS 0.35 ?m technology.


2014 ◽  
Vol 18 (2) ◽  
pp. 263-271
Author(s):  
Chulkyu Park ◽  
Kichang Jang ◽  
Hyojae Kim ◽  
Joongho Choi

Author(s):  
Rochelle Marie F. Amistoso ◽  
Michael Joe A. Bautista ◽  
Rafael Karlo D.P. Delos Santos ◽  
Joana Rochelle R. Ortiz ◽  
Louis P. Alarcon ◽  
...  

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