Concurrent Algorithm for High-Speed Point Multiplication in Elliptic Curve Cryptography

Author(s):  
Jun-Hong Chen ◽  
Ming-Der Shieh ◽  
Chien-Ming Wu
Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2126
Author(s):  
Muhammad Rashid ◽  
Malik Imran ◽  
Asher Sajid

This work presents an efficient high-speed hardware architecture for point multiplication (PM) computation of Elliptic-curve cryptography using binary fields over GF(2163) and GF(2571). The efficiency is achieved by reducing: (1) the time required for one PM computation and (2) the total number of required clock cycles. The required computational time for one PM computation is reduced by incorporating two modular multipliers (connected in parallel), a serially connected adder after multipliers and two serially connected squarer units (one after the first multiplier and another after the adder). To optimize the total number of required clock cycles, the point addition and point double instructions for PM computation of the Montgomery algorithm are re-structured. The implementation results after place-and-route over GF(2163) and GF(2571) on a Xilinx Virtex-7 FPGA device reveal that the proposed high-speed architecture is well-suited for the network-related applications, where millions of heterogeneous devices want to connect with the unsecured internet to reach an acceptable performance.


2021 ◽  
Vol 2021 ◽  
pp. 1-8
Author(s):  
Yong Xiao ◽  
Weibin Lin ◽  
Yun Zhao ◽  
Chao Cui ◽  
Ziwen Cai

Teleoperated robotic systems are those in which human operators control remote robots through a communication network. The deployment and integration of teleoperated robot’s systems in the medical operation have been hampered by many issues, such as safety concerns. Elliptic curve cryptography (ECC), an asymmetric cryptographic algorithm, is widely applied to practical applications because its far significantly reduced key length has the same level of security as RSA. The efficiency of ECC on GF (p) is dictated by two critical factors, namely, modular multiplication (MM) and point multiplication (PM) scheduling. In this paper, the high-performance ECC architecture of SM2 is presented. MM is composed of multiplication and modular reduction (MR) in the prime field. A two-stage modular reduction (TSMR) algorithm in the SCA-256 prime field is introduced to achieve low latency, which avoids more iterative subtraction operations than traditional algorithms. To cut down the run time, a schedule is put forward when exploiting the parallelism of multiplication and MR inside PM. Synthesized with a 0.13 um CMOS standard cell library, the proposed processor consumes 341.98k gate areas, and each PM takes 0.092 ms.


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