A High-Speed Elliptic Curve Cryptography Processor for Teleoperated Systems Security

Teleoperated robotic systems are those in which human operators control remote robots through a communication network. The deployment and integration of teleoperated robot’s systems in the medical operation have been hampered by many issues, such as safety concerns. Elliptic curve cryptography (ECC), an asymmetric cryptographic algorithm, is widely applied to practical applications because its far significantly reduced key length has the same level of security as RSA. The efficiency of ECC on GF (p) is dictated by two critical factors, namely, modular multiplication (MM) and point multiplication (PM) scheduling. In this paper, the high-performance ECC architecture of SM2 is presented. MM is composed of multiplication and modular reduction (MR) in the prime field. A two-stage modular reduction (TSMR) algorithm in the SCA-256 prime field is introduced to achieve low latency, which avoids more iterative subtraction operations than traditional algorithms. To cut down the run time, a schedule is put forward when exploiting the parallelism of multiplication and MR inside PM. Synthesized with a 0.13 um CMOS standard cell library, the proposed processor consumes 341.98k gate areas, and each PM takes 0.092 ms.

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A High-Performance Elliptic Curve Cryptographic Processor of SM2 over GF(p)

Electronics ◽

10.3390/electronics8040431 ◽

2019 ◽

Vol 8 (4) ◽

pp. 431 ◽

Cited By ~ 4

Author(s):

Xianghong Hu ◽

Xin Zheng ◽

Shengshi Zhang ◽

Weijun Li ◽

Shuting Cai ◽

...

Keyword(s):

Elliptic Curve ◽

High Performance ◽

Complementary Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Prime Field ◽

Practical Applications ◽

Public Key Cryptosystems ◽

Cell Library ◽

Multiplication Operation ◽

And Performance

Elliptic curve cryptography (ECC) is widely used in practical applications because ECC has far fewer bits for operands at the same level of security than other public-key cryptosystems such as RSA. The performance of an ECC processor is usually determined by modular multiplication (MM) and point multiplication (PM) operations. For recommended prime field, MM operation can consist of multiplication and fast reduction operations. In this paper, a 256-bit multiplication operation is implemented by a 129-bit (half-word) multiplier using Karatsuba–Ofman multiplication algorithm. The fast reduction is a modulo operation, which gets 512-bit input data from multiplication and outputs a 256-bit result ( 0 ≤ Z < p ) . We propose a two-stage fast reduction algorithm (TSFR) over SCA-256 prime field, which can obtain an intermediate result of 0 ≤ Z < 2 p instead of 0 ≤ Z < 14 p in traditional algorithm, avoiding a lot of repetitive subtraction operations. The PM operation is implemented in width nonadjacent form (NAF) algorithm and its operational schedules are improved to increase the parallelism of multiplication and fast reduction operations. Synthesized with a 0.13 μ m complementary metal oxide semiconductor (CMOS) standard cell library, the proposed processor costs an area of 280 k gates and PM operation takes 0.057 ms at the frequency of 250 MHz. The design is also implemented on Xilinx Virtex-6 platform, which consumes 27.655 k LUTs and takes 0.37 ms to perform one 256-bit PM operation, attaining six times speed-up over the state-of-the-art. The processor makes a tradeoff between area and performance, thus it is better than other methods.

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High performance hardware support for elliptic curve cryptography over general prime field

Microprocessors and Microsystems ◽

10.1016/j.micpro.2016.12.005 ◽

2017 ◽

Vol 51 ◽

pp. 331-342 ◽

Cited By ~ 16

Author(s):

Khalid Javeed ◽

Xiaojun Wang ◽

Mike Scott

Keyword(s):

Elliptic Curve ◽

Elliptic Curve Cryptography ◽

High Performance ◽

Hardware Support ◽

Prime Field

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Design and Implementation of High-Performance ECC Processor with Unified Point Addition on Twisted Edwards Curve

Sensors ◽

10.3390/s20185148 ◽

2020 ◽

Vol 20 (18) ◽

pp. 5148

Author(s):

Md. Mainul Islam ◽

Md. Selim Hossain ◽

Moh. Khalid Hasan ◽

Md. Shahjalal ◽

Yeong Min Jang

Keyword(s):

Elliptic Curve ◽

High Speed ◽

High Performance ◽

Security Level ◽

Prime Field ◽

Iot Security ◽

Point Multiplication ◽

Low Area ◽

Edwards Curve ◽

Twisted Edwards Curve

With the swift evolution of wireless technologies, the demand for the Internet of Things (IoT) security is rising immensely. Elliptic curve cryptography (ECC) provides an attractive solution to fulfill this demand. In recent years, Edwards curves have gained widespread acceptance in digital signatures and ECC due to their faster group operations and higher resistance against side-channel attacks (SCAs) than that of the Weierstrass form of elliptic curves. In this paper, we propose a high-speed, low-area, simple power analysis (SPA)-resistant field-programmable gate array (FPGA) implementation of ECC processor with unified point addition on a twisted Edwards curve, namely Edwards25519. Efficient hardware architectures for modular multiplication, modular inversion, unified point addition, and elliptic curve point multiplication (ECPM) are proposed. To reduce the computational complexity of ECPM, the ECPM scheme is designed in projective coordinates instead of affine coordinates. The proposed ECC processor performs 256-bit point multiplication over a prime field in 198,715 clock cycles and takes 1.9 ms with a throughput of 134.5 kbps, occupying only 6543 slices on Xilinx Virtex-7 FPGA platform. It supports high-speed public-key generation using fewer hardware resources without compromising the security level, which is a challenging requirement for IoT security.

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A Hardware-Accelerated ECDLP with High-Performance Modular Multiplication

International Journal of Reconfigurable Computing ◽

10.1155/2012/439021 ◽

2012 ◽

Vol 2012 ◽

pp. 1-14 ◽

Cited By ~ 4

Author(s):

Lyndon Judge ◽

Suvarna Mane ◽

Patrick Schaumont

Keyword(s):

Elliptic Curve ◽

Elliptic Curve Cryptography ◽

High Performance ◽

Design Space ◽

Discrete Logarithm ◽

Public Key Cryptography ◽

Modular Multiplication ◽

Polynomial Representation ◽

Prime Field ◽

Modular Multiplier

Elliptic curve cryptography (ECC) has become a popular public key cryptography standard. The security of ECC is due to the difficulty of solving the elliptic curve discrete logarithm problem (ECDLP). In this paper, we demonstrate a successful attack on ECC over prime field using the Pollard rho algorithm implemented on a hardware-software cointegrated platform. We propose a high-performance architecture for multiplication over prime field using specialized DSP blocks in the FPGA. We characterize this architecture by exploring the design space to determine the optimal integer basis for polynomial representation and we demonstrate an efficient mapping of this design to multiple standard prime field elliptic curves. We use the resulting modular multiplier to demonstrate low-latency multiplications for curves secp112r1 and P-192. We apply our modular multiplier to implement a complete attack on secp112r1 using a Nallatech FSB-Compute platform with Virtex-5 FPGA. The measured performance of the resulting design is 114 cycles per Pollard rho step at 100 MHz, which gives 878 K iterations per second per ECC core. We extend this design to a multicore ECDLP implementation that achieves 14.05 M iterations per second with 16 parallel point addition cores.

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