Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers

2007 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2007.378767 ◽

2007 ◽

Author(s):

Xiang Gao ◽

Eric A.M. Klumperink ◽

Bram Nauta

Keyword(s):

Clock Generation ◽

Phase Clock ◽

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A low-jitter skew-calibrated multi-phase clock generator for time-interleaved applications

2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) ◽

10.1109/isscc.2001.912690 ◽

2002 ◽

Author(s):

Lin Wu ◽

W.C. Black

Keyword(s):

Clock Generator ◽

Phase Clock ◽

Multi Phase ◽

Time Interleaved

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A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-32-9767-8_18 ◽

2019 ◽

pp. 202-214

Author(s):

Raviteja Kammari ◽

Vijaya Sankara Rao Pasupureddi

Keyword(s):

Delay Element ◽

Power Efficient ◽

Clock Generation ◽

Efficient Charge ◽

Phase Clock ◽

Multi Phase ◽

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A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers ◽

10.1109/isscc.2008.4523283 ◽

2008 ◽

Author(s):

Keng-Jan Hsiao ◽

Tai-Cheng Lee

Keyword(s):

Clock Generation ◽

Multiple Phase ◽

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A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) ◽

10.1109/iscas.2004.1328208 ◽

2004 ◽

Author(s):

Sai-Weng Sin ◽

Seng-Pan U ◽

R.P. Martins

Keyword(s):

Data Systems ◽

Sampled Data ◽

Clock Generation ◽

Phase Clock ◽

Multi Phase ◽

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Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test ◽

10.1109/vlsi-dat.2012.6212633 ◽

2012 ◽

Author(s):

Ruo-Ting Ding ◽

Shi-Yu Huang ◽

Chao-Wen Tzeng ◽

Shan-Chien Fang ◽

Chia-Chien Weng

Keyword(s):

Super Resolution ◽

Clock Generation ◽

Cyclic Property ◽

Phase Clock ◽

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A capacitive-coupling technique with phase noise and phase error reduction for multi-phase clock generation

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference ◽

10.1109/cicc.2014.6946098 ◽

2014 ◽

Author(s):

Feng Zhao ◽

Fa Foster Dai

Keyword(s):

Phase Noise ◽

Phase Error ◽

Error Reduction ◽

Capacitive Coupling ◽

Coupling Technique ◽

Clock Generation ◽

Phase Clock ◽

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Multi-Phase Clock Generation for Phase Interpolation With a Multi-Phase, Injection-Locked Ring Oscillator and a Quadrature DLL

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2021.3124486 ◽

2021 ◽

pp. 1-1

Author(s):

Zhaowen Wang ◽

Yudong Zhang ◽

Yuka Onizuka ◽

Peter R. Kinget

Keyword(s):

Ring Oscillator ◽

Clock Generation ◽

Phase Clock ◽

Multi Phase ◽

Phase Interpolation

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Design of Multi-phase Clock Generation and Selection Circuit for CDR

2009 WRI World Congress on Computer Science and Information Engineering ◽

10.1109/csie.2009.459 ◽

2009 ◽

Author(s):

Deng Junyong ◽

Jiang Lin ◽

Zeng Zecang

Keyword(s):

Clock Generation ◽

Phase Clock ◽

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A 14 GHz DLL based low-jitter multi-phase clock generator for low-band ultra-wideband application

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits APASIC-04 ◽

10.1109/apasic.2004.1349487 ◽

2004 ◽

Author(s):

Tsung-Te Liu ◽

Chorng-Kuang Wang

Keyword(s):

Ultra Wideband ◽

Clock Generator ◽

Phase Clock ◽

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Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications ◽

10.1109/tcsi.2006.869905 ◽

2006 ◽

Vol 53 (5) ◽

pp. 984-991 ◽

Author(s):

Ju-Ming Chou ◽

Yu-Tang Hsieh ◽

Jieh-Tsorng Wu

Keyword(s):

Clock Generation ◽

Phase Averaging ◽

Phase Clock ◽

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