GERARD: GEneral RApid Resolution of Digital Mazes Using a Memristor Emulator

Memristive technology is a promising game-changer in computers and electronics. In this paper, a system exploring the optimal paths through a maze, utilizing a memristor-based setup, is developed and concreted on a FPGA (field-programmable gate array) device. As a memristor, a digital emulator has been used. According to the proposed approach, the memristor is used as a delay element, further configuring the test graph as a memristor network. A parallel algorithm is then applied, successfully reducing computing time and increasing the system’s efficiency. The proposed system is simple, easy to scale up and capable of implementing different graph configurations. The operation of the algorithm in the MATLAB (matrix laboratory) programming enviroment is checked beforehand and then exported to two different Intel FPGAs: a DE0-Nano board and an Arria 10 GX 220 FPGA. In both cases, reliable results are obtained quickly and conveniently, even for the case of a 300 × 300 nodes maze.

GERARD: GEneral RApid Resolution of Digital Mazes Using a Memristor Emulator

In this paper, a system of searching for optimal paths is developed and concreted on a FPGA. It is based on a memristive emulator, used as a delay element, by configuring the test graph as a memristor network. A parallel algorithm is applied to reduce computing time and increase efficiency. The operation of the algorithm in Matlab is checked beforehand and then exported to two different Intel FPGAs: a DE0-Nano board and an Arria 10 GX 220 FPGA. In both cases reliable results are obtained quickly and conveniently, even for the case of a 300x300 nodes maze.

A 13-Bit, 12-ps Resolution Vernier Time-to-Digital Converter Based on Dual Delay-Rings for SPAD Image Sensor

A three-dimensional (3D) image sensor based on Single-Photon Avalanche Diode (SPAD) requires a time-to-digital converter (TDC) with a wide dynamic range and fine resolution for precise depth calculation. In this paper, we propose a novel high-performance TDC for a SPAD image sensor. In our design, we first present a pulse-width self-restricted (PWSR) delay element that is capable of providing a steady delay to improve the time precision. Meanwhile, we employ the proposed PWSR delay element to construct a pair of 16-stages vernier delay-rings to effectively enlarge the dynamic range. Moreover, we propose a compact and fast arbiter using a fully symmetric topology to enhance the robustness of the TDC. To validate the performance of the proposed TDC, a prototype 13-bit TDC has been fabricated in the standard 0.18-µm complementary metal–oxide–semiconductor (CMOS) process. The core area is about 200 µm × 180 µm and the total power consumption is nearly 1.6 mW. The proposed TDC achieves a dynamic range of 92.1 ns and a time precision of 11.25 ps. The measured worst integral nonlinearity (INL) and differential nonlinearity (DNL) are respectively 0.65 least-significant-bit (LSB) and 0.38 LSB, and both of them are less than 1 LSB. The experimental results indicate that the proposed TDC is suitable for SPAD-based 3D imaging applications.

Speed Fluctuation Suppression for the Inverter Compressor Based on the Adaptive Revised Repetitive Controller

Repetitive operation is extensively present in the inverter compressor refrigeration field. Research illustrates that an approximate periodic load disturbance deteriorates its self-sensing and efficiency in a low frequency range. According to an internal model theorem, a repetitive controller can realize periodic signal tracking or suppression; however, ideal repetitive control (IRC) can not be directly employed in practical application owing to its excessive sensitivity to period-time uncertainties or aperiodic component, etc. In addition, the ratio between period delay to sampling time can not always maintain an integer which causes the resonant frequencies to deviate from the interested. Even if the ratio is a fixed integer, the auxiliary function for stabilization in a conventional repetitive controller can result in the steady state tracking error. In this paper, a revised repetitive controller with a novel Savitzky–Golay (S–G) filter is proposed, the S–G filter cascaded with a traditional delay element can approximate the delay element with any ratio. Aiming at a different operating condition, a second order generalized integrator (SOGI) based observer is employed to extract disturbance fundamental component, and Steiglitz–McBride based adaptive notch filter (SM-ANF) is adopted for frequency estimation. The proposed scheme varies the S–G filter according to variable fundamental frequency and maintains its resonant frequencies corresponding with the fundamental and harmonic disturbance. In the end, simulations and experiments are implemented and results illustrate that speed fluctuation can be effectively suppressed by the proposed method.