Classification of IC Process Deformation Characteristics Using Memory Fail Bitmaps

Building a portfolio of deformations is the key step for building better defect models for the test and yield learning domain. A viable approach to achieve this goal is through geometric characterization and classification of failure patterns found on memory fail bitmaps. In this paper, we present preliminary results on how to build such a portfolio of deformations for an IC technology of interest based on a fail bitmap analysis study conducted on large, modern SRAM memory products.

Silicon Thinning using Ultra-Short Pulse Laser Ablation

Ultra-short pulse laser ablation is applied to IC backside sample preparation. It is contact-less, non-thermal, precise and can ablate the various types of material present in IC packages. This study concerns the optimization of ultra-short pulse laser ablation for silicon thinning. Uncontrolled silicon roughness and poor uniformity of the laser thinned cavity needed to be tackled. Special care is taken to minimize the silicon RMS roughness to less than 1µm. Application to sample preparation of 256Mbit devices is presented.

Fluorocarbon Precursor for High Aspect Ratio via Milling in Focused Ion Beam Modification of Integrated Circuits

Gas Assisted Etching (GAE) is the enabling technology for High Aspect Ratio (HAR) circuit access via milling in Focused Ion Beam (FIB) circuit modification. Metal interconnect layers of microelectronic Integrated Circuits (ICs) are separated by Inter-Layer Dielectric (ILD) materials, therefore HAR vias are typically milled in dielectrics. Most of the etching precursor gases presently available for GAE of dielectrics on commercial FIB systems, such as XeF2, Cl2, etc., are also effective etch enhancers for either Si, or/and some of the metals used in ICs. Therefore use of these precursors for via milling in dielectrics may lead to unwanted side effects, especially in a backside circuit edit approach. Making contacts to the polysilicon lines with traditional GAE precursors could also be difficult, if not impossible. Some of these precursors have a tendency to produce isotropic vias, especially in Si. It has been proposed in the past to use fluorocarbon gases as precursors for the FIB milling of dielectrics. Preliminary experimental evaluation of Trifluoroacetic (Perfluoroacetic) Acid (TFA, CF3COOH) as a possible etching precursor for the HAR via milling in the application to FIB modification of ICs demonstrated that highly enhanced anisotropic milling of SiO2 in HAR vias is possible. A via with 9:1 aspect ratio was milled with accurate endpoint on Si and without apparent damage to the underlying Si substrate.

Optimizing Gas-Assisted FIB Processes: The Importance of Oft-Ignored Secondary Parameters

The efficiency of Gas-Assisted Etching (GAE) and depositions performed using the Focused Ion Beam (FIB) technique is subject to numerous factors. Besides the wellknown primary parameters recommended by the FIB manufacturer (pixel spacing, dwell time, and gas pressures), certain secondary factors can also have a pronounced effect on the quality of these gas-assisted FIB operations. The position of the gas delivery nozzle during XeF2 mills on silicon is examined and was found to affect both the milling speed and the texture on the floor of the FIB trench. Limitations arising from the memory capacity of the FIB computer can also influence process times and trench quality. Exposing the FIB vacuum chamber to TMCTS during SiO2 depositions is found to temporarily impede the performance of subsequent tungsten depositions, especially following heavy or prolonged TMCTS exposure. A delay period may be required to achieve optimal tungsten depositions following TMCTS use. Finally, the focusing conditions of the ion beam are found to have a significant impact on the resistance of FIB-deposited metal films. This effect is attributed to partial milling of the deposition film due to the intense current density of the collimated ion beam. The resistances of metal depositions performed with intentionally defocused ion beams were found to be lower than those performed with focused beams.

Defect Snap Shot: Quick Isolation and Mapping of Interconnect Defects for Backend Yield Improvement

Metal interconnect defects have become a more serious yield detractor as backend process complexity has increased from a single layer to about 10 layers. This paper introduces a test methodology to monitor and localize the metal defects based on FPGA products. The test patterns are generated for each metal layer. The results not only indicate the severity of defects for each metal layer, but also accurately isolate open/short defects.

Backside Application of Acoustic Micro Imaging (AMI) on Plastic Ball Grid Array (PBGA) and Plastic Quad Flat Pack (PQFP) Packages

Acoustic Micro Imaging (AMI) is an established nondestructive technique for evaluation of electronic packages. Non-destructive evaluation of electronic packages is often a critical first step in the Failure Analysis (FA) process of semiconductor devices [1]. The molding compound to die surface interface of the Plastic Ball Grid Array (PBGA) and Plastic Quad Flat Pack (PQFP) packages is an important interface to acquire for the FA process. Occasionally, with these packages, the standard acoustic microscopy technique fails to identify defects at the molding compound to die surface interface. The hard to identify defects are found at the edge of the die next to the bond pads or under the bonds wires. This paper will present a technique, Backside Acoustic Micro Imaging (BAMI) analysis, which can better resolve the molding compound to die surface interface at the die edge by sending the acoustic signal through the backside of the PBGA and PQFP packages.

Advanced Acoustic Micro Imaging Applications: Deciphering Multiple Acoustic Echoes and Reflections

The acquisition of reliable Acoustic Micro Images (AMI) are an essential non-destructive step in the Failure Analysis (FA) of electronic packages. Advanced packaging and new IC materials present challenges to the collection of reliable AMI signals. The AMI is complicated due to new technologies that utilize an increasing number of interfaces in ICs and packages. We present two case studies in which it is necessary to decipher the acoustic echoes from the signals generated by the interface of interest in order to acquire trustworthy information about the IC package.

Characterization of Interconnect Defects Using Scanning Thermal Conductivity Microscopy

In this paper, scanning thermal conductivity microscopy is used to characterize interconnect defects due to electromigration. Similar features are observed both in the temperature and thermal conductivity micrographs. The key advantage of the thermal conductivity mode is that specimen bias is not required. This is an important advantage for the characterization of defects in large scale integrated circuits. The thermal conductivity micrographs of extrusion, exposed and subsurface voids are presented and compared with the corresponding topography and temperature micrographs.

Study of MFM Application in Semiconductor Failure Analysis

In this study we have investigated the magnetic field associated with a current flowing in a circuit using Magnetic Force Microscopy (MFM). The technique is able to identify the magnetic field associated with a current flow and has potential for failure analysis.

A Methodology for Characterizing System-Level ESD Sensitivity

Over the years, failures induced by an electrostatic discharge (ESD) have become a major concern for semiconductor manufacturers and electronic equipment makers. The ESD events that cause destructive failures have been studied extensively [1, 2]. However, not all ESD events cause permanent damage. Some events lead to recoverable failures that disrupt system functionality only temporarily (e.g. reboot, lockup, and loss of data). These recoverable failures are not as well understood as the ones causing permanent damage and tend to be ignored in the ESD literature [3, 4]. This paper analyzes and characterizes how these recoverable failures affect computer systems. An experimental methodology is developed to characterize the sensitivity of motherboards to ESD by simulating the systemlevel ESD events induced by computer users. The manuscript presents a case study where this methodology was used to evaluate the robustness of desktop computers to ESD. The method helped isolate several weak nets contributing to the failures and identified a design improvement. The result was that the robustness of the systems improved by a factor of 2.