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A case for standard-cell based RAMs in highly-ported superscalar processor structures
2017 18th International Symposium on Quality Electronic Design (ISQED)
◽
10.1109/isqed.2017.7918305
◽
2017
◽
Author(s):
Sungkwan Ku
◽
Elliott Forbes
◽
Rangeen Basu Roy Chowdhury
◽
Eric Rotenberg
Keyword(s):
Standard Cell
◽
Superscalar Processor
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References
Standard-Cell, Open-Architecture Power Conversion Systems
10.21236/ada468619
◽
2005
◽
Author(s):
D. Boroyevich
◽
F. Wang
◽
F. C. Lee
◽
W. G. Odendaal
◽
S. Edwards
Keyword(s):
Power Conversion
◽
Open Architecture
◽
Standard Cell
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Power and Variation Improved Near-Vt Standard Cell Library for 28-nm FDSOI
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
◽
10.1109/s3s46989.2019.9320687
◽
2019
◽
Author(s):
Wing-Tsi Wong
◽
Kamlesh Singh
◽
Jos Huisken
◽
Jose Pineda de Gyvez
Keyword(s):
Standard Cell
◽
Standard Cell Library
◽
Cell Library
◽
28 Nm
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24.4 A 5nm
[email protected]
and
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4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue
2021 IEEE International Solid- State Circuits Conference (ISSCC)
◽
10.1109/isscc42613.2021.9366000
◽
2021
◽
Author(s):
Hidehiro Fujiwara
◽
Yi-Hsin Nien
◽
Chih-Yu Lin
◽
Hsien-Yu Pan
◽
Hao-Wen Hsu
◽
...
Keyword(s):
Standard Cell
◽
Register File
Download Full-text
A 15000 Tuning Range Scalable Feed-Forward Oscillator With 0.05mm2 Area in CMOS Standard-Cell Format
2021 IEEE International Symposium on Circuits and Systems (ISCAS)
◽
10.1109/iscas51556.2021.9401776
◽
2021
◽
Author(s):
Julian Arenas
◽
Juan Sebastian Moya
◽
Elkim Roa
Keyword(s):
Tuning Range
◽
Standard Cell
◽
Feed Forward
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Superconductor Standard Cell Library for Advanced EDA Design Flow
IEEE Transactions on Applied Superconductivity
◽
10.1109/tasc.2021.3061024
◽
2021
◽
pp. 1-1
Author(s):
Sukanya Sagarika Meher
◽
Jushya Ravi
◽
Mustafa Eren Celik
◽
Stephen Miller
◽
Anubhav Sahu
◽
...
Keyword(s):
Design Flow
◽
Standard Cell
◽
Standard Cell Library
◽
Cell Library
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NMLib: A Nanomagnetic Logic Standard Cell Library
2021 IEEE International Symposium on Circuits and Systems (ISCAS)
◽
10.1109/iscas51556.2021.9401107
◽
2021
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Author(s):
Laysson Oliveira Luz
◽
Jose Augusto M. Nacif
◽
Ricardo S. Ferreira
◽
Omar P. Vilela Neto
Keyword(s):
Standard Cell
◽
Standard Cell Library
◽
Nanomagnetic Logic
◽
Cell Library
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Cross-Corner Delay Variation Model for Standard Cell Libraries
IEEE Access
◽
10.1109/access.2021.3080294
◽
2021
◽
pp. 1-1
Author(s):
Kwangsu Kim
◽
Byungha Joo
◽
Young Min Park
◽
Taeyang Jeong
◽
Ki Tae Kim
◽
...
Keyword(s):
Standard Cell
◽
Delay Variation
◽
Variation Model
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An EEPROM Supercell for Custom Standard Cell IC's
10.4271/871544
◽
1987
◽
Author(s):
Ernest Cordan
◽
Michael Eby
Keyword(s):
Standard Cell
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Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications
SN Computer Science
◽
10.1007/s42979-020-00328-3
◽
2020
◽
Vol 1
(6)
◽
Author(s):
R. K. Siddharth
◽
Y. B. Nithin Kumar
◽
M. H. Vasantha
Keyword(s):
Power Saving
◽
Standard Cell
◽
Flash Adc
◽
Power Saving Scheme
◽
Surveillance Applications
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Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm
Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09
◽
10.1145/1629911.1630042
◽
2009
◽
Cited By ~ 14
Author(s):
Weiguang Sheng
◽
Liyi Xiao
◽
Zhigang Mao
Keyword(s):
Genetic Algorithm
◽
Soft Error
◽
Gate Sizing
◽
Standard Cell
◽
Multi Objective
◽
Multi Objective Genetic Algorithm
◽
Error Optimization
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