A low-power 3.25GS/s 4th-order programmable analog FIR filter using split-CDAC coefficient multipliers for wideband analog signal processing

Since the memristor emerged as a programmable analog storage device, it has stimulated research on the design of analog/mixed-signal circuits with the memristor as the enabler of in-memory computation. Due to the difficulty in evaluating the circuit-level nonidealities of both memristors and CMOS devices, SPICE-accuracy simulation tools are necessary for perfecting the art of neuromorphic analog/mixed-signal circuit design. This article is dedicated to a native SPICE implementation of the memristor device models published in the open literature and develops case studies of applying such a circuit simulation with MOSFET models to study how device-level imperfections can make adversarial effects on the analog circuits that implement neuromorphic analog signal processing. Methods on memristor stamping in the framework of modified nodal analysis formulation are presented, and implementation results are reported. Furthermore, functional simulations on neuromorphic signal processing circuits including memristors and CMOS devices are carried out to validate the effectiveness of the native SPICE implementation of memristor models from the perspectives of simulation accuracy, efficiency, and convergence for large-scale simulation tasks.

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A Low-Power, High-Linearity Wideband 3.25 GS/s Fourth-Order Programmable Analog FIR Filter Using Split-CDAC Coefficient Multipliers

IEEE Transactions on Microwave Theory and Techniques ◽

10.1109/tmtt.2020.2967388 ◽

2020 ◽

Vol 68 (4) ◽

pp. 1576-1590 ◽

Cited By ~ 1

Author(s):

Shinwoong Park ◽

Dongseok Shin ◽

Kwang-Jin Koh ◽

Sanjay Raman

Keyword(s):

Low Power ◽

Fourth Order ◽

Fir Filter ◽

High Linearity ◽

Programmable Analog ◽

Coefficient Multipliers

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Design of Analog Signal Processing Applications Using Carbon Nanotube Field Effect Transistor-Based Low-Power Folded Cascode Operational Amplifier

Journal of Nanotechnology ◽

10.1155/2018/2301421 ◽

2018 ◽

Vol 2018 ◽

pp. 1-15 ◽

Cited By ~ 2

Author(s):

Varsha S. Bendre ◽

A. K. Kureshi ◽

Saurabh Waykole

Keyword(s):

Signal Processing ◽

Carbon Nanotube ◽

Low Power ◽

Operational Amplifier ◽

Field Effect ◽

Field Effect Transistors ◽

Analog Signal Processing ◽

Analog Signal ◽

Zero Crossing ◽

Folded Cascode

Carbon nanotube (CNT) is one of the embryonic technologies within recent inventions towards miniaturization of semiconductor devices and is gaining much attention due to very high throughput and very extensive series of applications in various analog/mixed signal applications of today’s high-speed era. The carbon nanotube field effect transistors (CNFETs) have been reconnoitred as the stimulating aspirant for the future generations of integrated circuit (IC) devices. CNFETs are being widely deliberated as probable replacement to silicon MOSFETs also. In this paper, different analog signal processing applications such as inverting amplifier, noninverting amplifier, summer, subtractor, differentiator, integrator, half-wave and full-wave rectifiers, clipper, clamper, inverting and noninverting comparators, peak detector, and zero crossing detector are implemented using low-power folded cascode operational amplifier (op-amp) implemented using CNFET. The proposed CNFET-based analog signal processing applications are instigated at 32 nm technology node. Simulation results show that the proposed applications are properly implemented using novel folded cascode operational amplifier (FCOA) implemented using CNFET.

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