A network on chip architecture and design methodology

2003 ◽  
Author(s):  
S. Kumar ◽  
A. Jantsch ◽  
J.-P. Soininen ◽  
M. Forsell ◽  
M. Millberg ◽  
...  
Keyword(s):  
Design Methodology ◽  
Network On Chip ◽  
On Chip ◽  
Architecture And Design

scholarly journals Timing-Error-Tolerant Network-on-Chip Design Methodology

2007 ◽  
Vol 26 (7) ◽  
pp. 1297-1310 ◽  
Author(s):  
Rutuparna Tamhankar ◽  
Srinivasan Murali ◽  
Stergios Stergiou ◽  
Antonio Pullini ◽  
Federico Angiolini ◽  
...  
Keyword(s):  
Design Methodology ◽  
Network On Chip ◽  
Timing Error ◽  
Chip Design ◽  
On Chip

scholarly journals A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias

2016 ◽  
Vol 43 ◽  
pp. 26-46 ◽  
Author(s):  
Mostafa Said ◽  
Ahmed Shalaby ◽  
Farhad Mehdipour ◽  
Morteza Biglari-Abhari ◽  
Mohamed El-Sayed
Keyword(s):  
Design Methodology ◽  
Network On Chip ◽  
Through Silicon Vias ◽  
3D Network ◽  
On Chip ◽  
Silicon Vias

QNoC: QoS architecture and design process for network on chip

2004 ◽  
Vol 50 (2-3) ◽  
pp. 105-128 ◽  
Author(s):  
Evgeny Bolotin ◽  
Israel Cidon ◽  
Ran Ginosar ◽  
Avinoam Kolodny
Keyword(s):  
Design Process ◽  
Network On Chip ◽  
Qos Architecture ◽  
On Chip ◽  
Architecture And Design
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