QNoC: QoS architecture and design process for network on chip

2004 ◽  
Vol 50 (2-3) ◽  
pp. 105-128 ◽  
Author(s):  
Evgeny Bolotin ◽  
Israel Cidon ◽  
Ran Ginosar ◽  
Avinoam Kolodny
Keyword(s):  
Design Process ◽  
Network On Chip ◽  
Qos Architecture ◽  
On Chip ◽  
Architecture And Design

scholarly journals Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology

2011 ◽  
Author(s):  
S Le Beux ◽  
J Trajkovic ◽  
I O'Connor ◽  
G Nicolescu ◽  
G Bois ◽  
...  
Keyword(s):  
Design Methodology ◽  
Network On Chip ◽  
Ring Network ◽  
On Chip ◽  
Architecture And Design ◽  
Optical Ring

scholarly journals Applying Genetic Algorithm to Solve Partitioning and Mapping Problem for Mesh Network-on-Chip Systems

2021 ◽  
Vol 13 (1) ◽  
pp. 33-47
Author(s):  
Walid Mokthar Salh ◽  
Azeddien M. Sllame
Keyword(s):  
Genetic Algorithm ◽  
Power Consumption ◽  
Design Process ◽  
Network On Chip ◽  
Experimental Results ◽  
Mesh Network ◽  
Data Dependencies ◽  
Mapping Problem ◽  
Mesh Topology ◽  
On Chip

This paper presents a genetic based approach to the partitioning and mapping of multicore SoC cores over a NoC system that uses mesh topology. The proposed algorithm performs the partitioning and mapping by reducing communication cost and minimizing power consumption by placing those intercommunicated cores as close as possible together. A program developed in C++ in which the provided specification of the multicore MPSoC system captures all data dependencies before any start of the design process. Experimental results of several multimedia benchmarks demonstrates that the genetic-based approach able to find different satisfied implementations to the problem of partitioning and mapping of MPSoC cores over mesh-based NoC system that satisfies design goals.

VLSI Design Of Low Energy Modeling For Network On Chip (NoC) Applications

2014 ◽  
Vol 5 (1) ◽  
pp. 27-32
Author(s):  
Jeeva Anusha ◽  
◽  
V. Thrimurthulu ◽  
Keyword(s):  
Vlsi Design ◽  
Network On Chip ◽  
Energy Modeling ◽  
Low Energy ◽  
On Chip

Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

2014 ◽  
Vol 35 (2) ◽  
pp. 341-346
Author(s):  
Xiao-fu Zheng ◽  
Hua-xi Gu ◽  
Yin-tang Yang ◽  
Zhong-fan Huang
Keyword(s):  
Network On Chip ◽  
Low Latency ◽  
Router Architecture ◽  
On Chip
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