Energy Efficient Architectures for the Log-MAP Decoder through Intelligent Memory Usage

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) ◽

10.1109/isvlsi.2005.29 ◽

2005 ◽

Author(s):

I. Atluri ◽

A.K. Kumaraswamy

Keyword(s):

Energy Efficient ◽

Memory Usage ◽

Intelligent Memory ◽

Map Decoder ◽

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FPGA Implementation of an Efficient High Speed Max-log-MAP Decoder

2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI) ◽

10.1109/icacci.2018.8554365 ◽

2018 ◽

Author(s):

Aishwarya Ambat ◽

Karthi Balasubramanian ◽

B. Yamuna ◽

Deepak Mishra

Keyword(s):

Fpga Implementation ◽

Map Decoder ◽

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A high-troughput radix-4 log-MAP decoder with low complexity LLR architecture

2009 International Symposium on VLSI Design, Automation and Test ◽

10.1109/vdat.2009.5158137 ◽

2009 ◽

Author(s):

Hsiang-Tsung Chuang ◽

Kai-Hsin Tseng ◽

Wai-Chi Fang

Keyword(s):

Low Complexity ◽

Map Decoder ◽

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New VLSI design of a max-log-MAP decoder

The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004. ◽

10.1109/newcas.2004.1359009 ◽

2004 ◽

Author(s):

L. Sabeti ◽

M. Ahmadi ◽

K. Tepe

Keyword(s):

Vlsi Design ◽

Map Decoder ◽

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A 952MS/s Max-Log MAP Decoder Chip using Radix-4 × 4 ACS Architecture

2006 IEEE Asian Solid-State Circuits Conference ◽

10.1109/asscc.2006.357856 ◽

2006 ◽

Author(s):

Cheng-Hao Tang ◽

Cheng-Chi Wong ◽

Chih-Lung Chen ◽

Chien-Ching Lin ◽

Hsie-Chia Chang

Keyword(s):

Map Decoder ◽

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Effect of Hardware Trojans on a Low Power and Area Efficient Max-log-MAP Decoder

2018 7th International Conference on Reliability, Infocom Technologies and Optimization (Trends and Future Directions) (ICRITO) ◽

10.1109/icrito.2018.8748533 ◽

2018 ◽

Author(s):

V Arul Jothi ◽

Karthi Balasubramanian ◽

B. Yamuna

Keyword(s):

Low Power ◽

Hardware Trojans ◽

Map Decoder ◽

Log Map ◽

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VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder

Journal of Low Power Electronics ◽

10.1166/jolpe.2015.1391 ◽

2015 ◽

Vol 11 (3) ◽

pp. 406-412 ◽

Author(s):

Rahul Shrestha ◽

Roy P. Paily

Keyword(s):

Energy Efficient ◽

Hardware Implementation ◽

Vlsi Design ◽

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A 6.6pJ/bit/iter radix-16 modified log-MAP decoder using two-stage ACS architecture

IEEE Asian Solid-State Circuits Conference 2011 ◽

10.1109/asscc.2011.6123575 ◽

2011 ◽

Author(s):

Kai-Ting Shr ◽

Yu-Cheng Chang ◽

Chu-Yi Lin ◽

Yuan-Hao Huang

Keyword(s):

Two Stage ◽

Map Decoder ◽

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A Novel Metric Representation for Low-Complexity Log-Map Decoder

2005 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2005.1465964 ◽

2005 ◽

Author(s):

Byonghyo Shim ◽

H.G. Myung

Keyword(s):

Low Complexity ◽

Map Decoder ◽

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Simplified max-log-MAP decoder structure

Joint IST Workshop on Mobile Future, 2006 and the Symposium on Trends in Communications. SympoTIC '06. ◽

10.1109/tic.2006.1708009 ◽

2006 ◽

Author(s):

P. Salmela ◽

T. Jarvinen ◽

J. Takala

Keyword(s):

Map Decoder ◽

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A Multiple-Radix MAP-Decoder Microarchitecture and Its ASIC Implementation for Energy-Efficient and Variable-Throughput Applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2020.3031001 ◽

2021 ◽

Vol 29 (1) ◽

pp. 65-75

Author(s):

Rahul Shrestha

Keyword(s):

Energy Efficient ◽

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