An Adaptive Kalman Filter based Digital Phase Detector for All Digital Phase-Locked Loop

2021 ◽  
Author(s):  
Ke Wu ◽  
Chenyue Shi ◽  
Yuchen Li ◽  
Changzhan Gu ◽  
Jinjing
Keyword(s):  
Kalman Filter ◽  
Phase Locked Loop ◽  
Phase Detector ◽  
Adaptive Kalman Filter ◽  
Digital Phase

An Example of a Low-Cost Phase-Locked-Loop Digital Phase Detector

1995 ◽  
Vol 28 (18) ◽  
pp. 131-133
Author(s):  
Paulo Roberto Brero De Campos ◽  
Álvaro Geraldo Badan Palhares
Keyword(s):  
Low Cost ◽  
Phase Locked Loop ◽  
Phase Detector ◽  
Digital Phase

scholarly journals Comparing Digital Phase-Locked Loop and Kalman Filter for Clock Tracking in Ultrawideband Location System

2018 ◽  
Vol 2018 ◽  
pp. 1-5
Author(s):  
Qian Gao ◽  
Chong Shen ◽  
Kun Zhang
Keyword(s):  
Kalman Filter ◽  
Phase Locked Loop ◽  
Structure And Properties ◽  
Synchronization System ◽  
Location System ◽  
Digital Phase ◽  
Clock Correction

For timing and synchronization system, digital phase-locked loop (DPLL) and Kalman filter all have been widely used as the clock tracking and clock correction schemes for the similar structure and properties. This paper compares the two schemes used for ultrawideband (UWB) location system. The improved Kalman filter is more immune to interference.

scholarly journals Design of All Digital Phase Locked Loop for Wireless Applications

2018 ◽  
Vol 7 (3.12) ◽  
pp. 836
Author(s):  
Swetha R ◽  
J Manjula ◽  
A Ruhan bevi
Keyword(s):  
Frequency Synthesizer ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Phase Detector ◽  
Ring Oscillator ◽  
Frequency Range ◽  
Loop Filter ◽  
Wireless Applications ◽  
Digital Phase ◽  
Operating Frequency Range

This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO). The programmable divider is used in the feed-back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW. 

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