scholarly journals Design of All Digital Phase Locked Loop for Wireless Applications

2018 ◽  
Vol 7 (3.12) ◽  
pp. 836
Author(s):  
Swetha R ◽  
J Manjula ◽  
A Ruhan bevi
Keyword(s):  
Frequency Synthesizer ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Phase Detector ◽  
Ring Oscillator ◽  
Frequency Range ◽  
Loop Filter ◽  
Wireless Applications ◽  
Digital Phase ◽  
Operating Frequency Range

This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO). The programmable divider is used in the feed-back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW. 

Design of Broadband, High-Speed Dual-Modulus Prescaler for Multi-Mode PLL Frequency Synthesizer

2013 ◽  
Vol 364 ◽  
pp. 439-443
Author(s):  
Xue Fei Jiang ◽  
Xiang Ning Fan
Keyword(s):  
Circuit Design ◽  
High Speed ◽  
Frequency Synthesizer ◽  
Cmos Technology ◽  
Frequency Range ◽  
Dual Mode ◽  
Hardware Cost ◽  
Operating Frequency Range ◽  
Pll Frequency Synthesizer ◽  
Multi Mode

A architecture of multi-mode PLL frequency synthesizer one can meet a variety of communication standards is presented in this paper, which can provide each mode with the required frequency, while reducing the system's hardware cost. Optimized broadband high-speed dual-mode prescaler (DMP)'s internal structure, the principle of circuit design and its layout is introduced. The DMP is produced by 0.18μm CMOS technology. The post simulation results show that with the 1.8V power, the DMP's operating frequency range is 0.4 ~ 9.6GHz, the power consumption is 7.6mA.

Low Power, Wide Range Synthesizer for 534MHz–18.56GHz Band with FoM of −192.45dBc/Hz

2021 ◽  
pp. 2250032
Author(s):  
Gaurav Kumar Sharma ◽  
Arun Kishor Johar ◽  
D. Boolchandani
Keyword(s):  
Figure Of Merit ◽  
Satellite Communication ◽  
Frequency Synthesizer ◽  
Supply Voltage ◽  
Wide Spectrum ◽  
Charge Pump ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
Loop Filter ◽  
Wide Range

A wide range frequency synthesizer is designed with the help of dual voltage tunable Differential Ring Oscillator (DRO). Frequency ranging from 534[Formula: see text]MHz to 18.56[Formula: see text]GHz can be generated using the proposed synthesizer. As proposed circuit utilizes dual voltage tunable DRO, a select input is provided to control the output frequency range. Logic low value (0[Formula: see text]V) of select input generates frequencies from 534[Formula: see text]MHz to 5.08[Formula: see text]GHz whereas logic high value (1.1[Formula: see text]V) of select input enables the frequency generation in the range of 5.08[Formula: see text]GHz to 18.56[Formula: see text]GHz. This work utilizes a single charge pump and single loop filter along with charge pump and bias control circuit. Proposed circuit is designed in GPDK 45-nm CMOS technology with supply voltage of 1.1[Formula: see text]V. Power consumption of the proposed circuits is 2.88[Formula: see text]mW while generating frequency of 7.84[Formula: see text]GHz. Proposed synthesizer demonstrates Figure of Merit (FoM2) of [Formula: see text][Formula: see text]dBc/Hz at this frequency. Because of such a wide spectrum, this synthesizer is well suited in the field of satellite communication, GPS and navigation.

Research on the Compound Frequency Tracking Mode of Ultrasonic Power Based on DSP

2014 ◽  
Vol 1027 ◽  
pp. 257-261
Author(s):  
Chang You Li ◽  
Xiao Qian Wu ◽  
Ming Ming Jia
Keyword(s):  
Phase Locked Loop ◽  
Phase Detector ◽  
Ultrasonic Power ◽  
Frequency Range ◽  
Frequency Tracking ◽  
Digital Phase ◽  
Tracking Mode ◽  
Tracking Technology ◽  
Tracking Strategy ◽  
Modal Resonance

Aiming at the problem that the tracking frequency range of ultrasonic power is fixed, and the accuracy of tacking frequency is low, the tactics of digital phase-locked loop frequency tracking technology combined with changing step searching circuit peak is proposed. The frequency tracking is achieved by combining the advantages of digital phase-locked loop frequency tracking technology with changing step searching circuit peak, building the digital phase detector circuit and current effective value converter circuit, taking the feedback of sampling the phase and circuit peak as basic of frequency tracking. Build the simulating model in Multisim. The experiment results show that composite frequency tracking strategy can effectively achieve frequency tracking and dynamically lock transducer multi-modal resonance.

scholarly journals Design of area-efficient GHz range current mode frequency synthesizer using standard CMOS technology

2019 ◽  
Vol 70 (4) ◽  
pp. 323-328
Author(s):  
Dan-Dan Zheng ◽  
Yu-Bin Li ◽  
Chang-Qi Wang ◽  
Kai Huang ◽  
Xiao-Peng Yu
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Mode Frequency ◽  
Loop Filter ◽  
Silicon Area ◽  
Power Efficient ◽  
A Current

Abstract In this paper, an area and power efficient current mode frequency synthesizer for system-on-chip (SoC) is proposed. A current-mode transformer loop filter suitable for low supply voltage is implemented to remove the need of a large capacitor in the loop filter, and a current controlled oscillator with additional voltage based frequency tuning mechanism is designed with an active inductor. The proposed design is further integrated with a fully programmable frequency divider to maintain a good balance among output frequency operating range, power consumption as well as silicon area. A test chip is implemented in a standard 0.13 µm CMOS technology, measurement result demonstrates that the proposed design has a working range from 916 MHz to 1.1 l GHz and occupies a silicon area of 0.25 mm2 while consuming 8.4 mW from a 1.2 V supply.

Analysis and Design of High Performance Phase Frequency Detector, Charge Pump and Loop Filter Circuits for Phase Locked Loop in Wireless Applications

2016 ◽  
Vol 4 (2) ◽  
pp. 397
Author(s):  
P.N. Metange ◽  
K. B. Khanchandani
Keyword(s):  
Leakage Current ◽  
High Performance ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Loop Filter ◽  
Phase Frequency Detector ◽  
Analysis And Design ◽  
Wireless Applications ◽  
5 Ghz ◽  
Frequency Detector

<p>This paper presents the analysis and design of high performance phase frequency detector, charge pump and loop filter circuits for phase locked loop in wireless applications. The proposed phase frequency detector (PFD) consumes only 8 µW and utilises small area. Also, at 1.8V voltage supply the maximum operation frequency of the conventional PFD is 500 MHz whereas proposed PFD is 5 GHz. Hence, highly suitable for low power, high speed and low jitter applications.  The differential charge pump uses switches using NMOS and the inverter delays for up and down signals do not generate any offset due to its fully symmetric operation. This configuration doubles the range of output voltage compliance compared to single ended charge pump. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. All the circuits are implemented using cadence 0.18 μm CMOS Process.</p>

scholarly journals DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW

2019 ◽  
Vol 82 (1) ◽  
Author(s):  
Florence Choong ◽  
Mamun Ibne Reaz ◽  
Mohamad Ibrahim Kamaruzzaman ◽  
Md. Torikul Islam Badal ◽  
Araf Farayez ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Process Technology ◽  
Chip Area ◽  
Digital Phase ◽  
Low Power Dissipation

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL.

scholarly journals A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Bandwidth Control

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 109
Author(s):  
Youming Zhang ◽  
Xusheng Tang ◽  
Zhennan Wei ◽  
Kaiye Bao ◽  
Nan Jiang
Keyword(s):  
Phase Noise ◽  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Chip Area ◽  
Loop Bandwidth ◽  
Bandwidth Control ◽  
Ku Band

This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.

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