Digital phase locked loop (DPLL) with offset dithered bang-bang phase detector (BBPD) for bandwidth control

Author(s):  
Younghoon Kim ◽  
Min-Ki Jeon ◽  
Changsik Yoo
1995 ◽  
Vol 28 (18) ◽  
pp. 131-133
Author(s):  
Paulo Roberto Brero De Campos ◽  
Álvaro Geraldo Badan Palhares

2018 ◽  
Vol 7 (3.12) ◽  
pp. 836
Author(s):  
Swetha R ◽  
J Manjula ◽  
A Ruhan bevi

This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO). The programmable divider is used in the feed-back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW. 


2014 ◽  
Vol 1027 ◽  
pp. 257-261
Author(s):  
Chang You Li ◽  
Xiao Qian Wu ◽  
Ming Ming Jia

Aiming at the problem that the tracking frequency range of ultrasonic power is fixed, and the accuracy of tacking frequency is low, the tactics of digital phase-locked loop frequency tracking technology combined with changing step searching circuit peak is proposed. The frequency tracking is achieved by combining the advantages of digital phase-locked loop frequency tracking technology with changing step searching circuit peak, building the digital phase detector circuit and current effective value converter circuit, taking the feedback of sampling the phase and circuit peak as basic of frequency tracking. Build the simulating model in Multisim. The experiment results show that composite frequency tracking strategy can effectively achieve frequency tracking and dynamically lock transducer multi-modal resonance.


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