In this paper, the design of a CMOS transceiver circuits for CAN bus based on 0.5μm n-well CMOS process is presented. It has the advantages of high speed, high driving capability and strong anti-interference capability. It is mainly made up of a receiver and a transmitter which includes the input stage circuit, the middle stage circuit, the slew rate control circuit and the output stage circuit. With five cascaded inverters, the middle stage circuit can provide a high driving current and a small delay. In the slew rate control circuit, due to a variable charge or discharge current source, the slew rate of output signal could be adjusted continuously by an external resistance Rs. So it is very convenient for the chip to be applied in different modes and at different rates. The output stage circuit has the function of short-circuit protection, overvoltage and undervoltage protection. The receiver circuit is a hysteresis comparator introduced by a positive feedback to reduce the differential noise effectively, and it has a small temperature coefficient too. Hspice simulation results show that the transceiver meets the ISO-11898 standards and could operate at the rate of 1Mbit/s.
Power optimal gate current profiles for the slew rate control of Smart Power ICs