Gate Driver Circuits With Discrete Components For GaN-based Multi-Level Multi-Inductor Hybrid Converter

<p>Gate driver circuits to ensure proper turn-on and turn-off for power switches are essential parts of a power converter design. They become even more important for multilevel converters where multiple switches are operated at active voltage domains. Recent favorable use of Gallium-Nitride (GaN) devices for power switches makes gate driving even more challenging as the switch performance and reliability are more sensitive to variations of the gate driving signals and power compared with traditional power MOSFETs. This paper discusses gate driving methods using a multi-level multi-inductor hybrid (MIH) converter as the demonstration prototype to address two key challenges in designing gate drivers: 1) providing level-shifted PWM signals to active voltage domains and 2) powering schemes for gate driver circuits. To solve the first challenge, an optimal use of available half-bridge drivers is devised to eliminate the need for separate signal isolator chips. This method was implemented and verified in a MIH converter prototype for 48-V Point-of-Load (PoL) applications using three different powering schemes for gate drivers, including isolated power modules, regulated supplies from switch blocking voltages, and cascaded bootstrap power rails with regulations. The gate driver techniques and powering schemes are compared experimentally in terms of performance to illustrate their benefits and trade-offs.</p>

Gate Driver Circuits With Discrete Components For GaN-based Multi-Level Multi-Inductor Hybrid Converter

<p>Gate driver circuits to ensure proper turn-on and turn-off for power switches are essential parts of a power converter design. They become even more important for multilevel converters where multiple switches are operated at active voltage domains. Recent favorable use of Gallium-Nitride (GaN) devices for power switches makes gate driving even more challenging as the switch performance and reliability are more sensitive to variations of the gate driving signals and power compared with traditional power MOSFETs. This paper discusses gate driving methods using a multi-level multi-inductor hybrid (MIH) converter as the demonstration prototype to address two key challenges in designing gate drivers: 1) providing level-shifted PWM signals to active voltage domains and 2) powering schemes for gate driver circuits. To solve the first challenge, an optimal use of available half-bridge drivers is devised to eliminate the need for separate signal isolator chips. This method was implemented and verified in a MIH converter prototype for 48-V Point-of-Load (PoL) applications using three different powering schemes for gate drivers, including isolated power modules, regulated supplies from switch blocking voltages, and cascaded bootstrap power rails with regulations. The gate driver techniques and powering schemes are compared experimentally in terms of performance to illustrate their benefits and trade-offs.</p>

Cascaded Smart Gate Drivers for Modular Multilevel Converters Control: A Decentralized Voltage Balancing Algorithm

Recent Modular Multilevel Converter (MMC) topology allows for drastic improvements in power electronic conversion such as higher energy quality, lower power semiconductors electrical stress, decreased Electro-Magnetic Interferences (EMI), and reduced switching losses. MMC is widely used in High Voltage Direct-Current (HVDC) transmissions as it offers, theoretically, no voltage limit. However, its control electronic structure is not modular itself. Especially, the insulation voltage between the submodule gate drivers’ primaries and secondaries depends on the number of submodules. The converter voltage levels cannot be increased without designing all gate driver isolations again. To solve that issue, the novel concept of distributed galvanic insulation is introduced for multilevel converters. The submodule’s gate drivers are daisy-chained, which naturally reduces the insulation voltage to the submodule capacitor voltage, regardless of the number of submodules. The MMC becomes truly modular as the number of submodules can be increased without impacting on the previous control electronic circuit. Such an innovative control structure weakens the link between the main control unit and the gate drivers. This inherent structural problem can be solved through the use of Smart-Gate Drivers (SGD), as they are often equipped with fast and bidirectional communication channels, while highly increasing the converter reliability. The innovation proposed in that work is the involvement of smart gate drivers in the distributed galvanic insulation-based MMC control and monitoring. First, the numerous benefits of smart gate drivers are discussed. Then, an innovative Voltage Balancing Algorithm directly integrated on the chained gate drivers is proposed and detailed. It features a tunable parameter, offering a trade-off between accurate voltage balancing and execution time. The proposed embedded algorithm features a low execution time due to simultaneous voltage comparisons. Such an algorithm is executed by the gate drivers themselves, relieving the main control unit in an original decentralized control scheme. A simulation model of a multi-megawatts three-phase grid-tied MMC inverter is realized, allowing validation of the proposed algorithm. Matlab/Simulink logic blocs allow us to simulate a typical CPLD/FPGA component, often embedded on smart gate drivers. The converter with the proposed embedded algorithm is simulated in steady-state and during load impact. The controlled delay and slew rate inferred by the algorithm do not disturb the converter behavior, allowing its conceptual validation.