A 103-dB SFDR Calibration-Free Oversampled SAR ADC With Mismatch Error Shaping and Pre-Comparison Techniques

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2021.3135559 ◽

2021 ◽

pp. 1-1

Author(s):

Yuting Shen ◽

Hanyue Li ◽

Haoming Xin ◽

Eugenio Cantatore ◽

Pieter Harpe

Keyword(s):

Sar Adc ◽

Mismatch Error ◽

Calibration Free

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A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4x Passive Gain and Second-Order DAC Mismatch Error Shaping

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2021.3087661 ◽

2021 ◽

pp. 1-1

Author(s):

Jiaxin Liu ◽

Xing Wang ◽

Zijie Gao ◽

Mingtao Zhan ◽

Xiyuan Tang ◽

...

Keyword(s):

Second Order ◽

Sar Adc ◽

Noise Shaping ◽

Mismatch Error ◽

Calibration Free ◽

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A low-cost 0.98μW0.8V oversampled SAR ADC with pre-comparison and mismatch error shaping achieving 84.5dB SNDR and 103dB SFDR

2021 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc51472.2021.9431475 ◽

2021 ◽

Author(s):

Yuting Shen ◽

Hanyue Li ◽

Haoming Xin ◽

Eugenio Cantatore ◽

Pieter Harpe

Keyword(s):

Low Cost ◽

Sar Adc ◽

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An Amplifier-Less Calibration-Free SAR ADC Achieving >100dB SNDR for Multi-Channel ECG Acquisition with 667mVpp Linear Input Range

2019 Symposium on VLSI Circuits ◽

10.23919/vlsic.2019.8777944 ◽

2019 ◽

Author(s):

Wei-Hsiang Huang ◽

Su-Hao Wu ◽

Zhi-Xin Chen ◽

Yun-Shiang Shu

Keyword(s):

Sar Adc ◽

Input Range ◽

Calibration Free

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20.3 A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4th-Order Noise-Shaping SAR ADC

2019 IEEE International Solid- State Circuits Conference - (ISSCC) ◽

10.1109/isscc.2019.8662313 ◽

2019 ◽

Author(s):

Lu Jie ◽

Boyi Zheng ◽

Michael P. Flynn

Keyword(s):

Sar Adc ◽

Free Time ◽

Noise Shaping ◽

Calibration Free ◽

Time Interleaved

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An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2016.2592623 ◽

2016 ◽

Vol 51 (12) ◽

pp. 2928-2940 ◽

Author(s):

Yun-Shiang Shu ◽

Liang-Ting Kuo ◽

Tien-Yu Lo

Keyword(s):

Sar Adc ◽

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16.4 A Calibration-Free 71.7dB SNDR 100MS/s 0.7mW Weighted-Averaging Correlated Level Shifting Pipelined SAR ADC with Speed-Enhancement Scheme

2020 IEEE International Solid- State Circuits Conference - (ISSCC) ◽

10.1109/isscc19947.2020.9063055 ◽

2020 ◽

Author(s):

Tsung-Chih Hung ◽

Jia-Ching Wang ◽

Tai-Haur Kuo

Keyword(s):

Sar Adc ◽

Weighted Averaging ◽

Calibration Free ◽

Correlated Level Shifting

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An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2021.3087660 ◽

2021 ◽

pp. 1-11

Author(s):

Chuanshi Yang ◽

Erik Olieman ◽

Alphons Litjes ◽

Lei Qiu ◽

Kai Tang ◽

...

Keyword(s):

Sar Adc ◽

Mismatch Error ◽

Shaping Technique ◽

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A 16-Bit Calibration-Free SAR ADC With Binary-Window and Capacitor-Swapping DAC Switching Schemes

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2021.3096242 ◽

2021 ◽

pp. 1-12

Author(s):

Yung-Hui Chung ◽

Chia-Hui Tien ◽

Qi-Feng Zeng

Keyword(s):

Sar Adc ◽

Calibration Free

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A 12-bit 40-MS/s calibration-free SAR ADC

2017 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2017.8050307 ◽

2017 ◽

Author(s):

Chung-Wei Hsu ◽

Li-Jen Chang ◽

Chun-Po Huang ◽

Soon-Jyh Chang

Keyword(s):

Sar Adc ◽

Calibration Free

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A 12-b 40-MS/s Calibration-Free SAR ADC

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2017.2771364 ◽

2018 ◽

Vol 65 (3) ◽

pp. 881-890 ◽

Author(s):

Chung-Wei Hsu ◽

Soon-Jyh Chang ◽

Chun-Po Huang ◽

Li-Jen Chang ◽

Ya-Ting Shyu ◽

...

Keyword(s):

Sar Adc ◽

Calibration Free

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