Four dimensional hyperchaotic communication system based on dynamic feedback synchronization technique for image encryption systems

<span>This paper presents the design and simulation of a hyperchaotic communication system based on four dimensions (4D) Lorenz generator. The synchronization technique that used between the master/transmitter and the slave/receiver is based on dynamic feedback modulation technique (DFM). The mismatch error between the master dynamics and slave dynamics are calculated continuously to maintain the sync process. The information signal (binary image) is masked (encrypted) by the hyperchaotic sample x of Lorenz generator. The design and simulation of the overall system are carried out using MATLAB Simulink software. The simulation results prove that the system is suitable for securing the plain-data, in particular the image data with a size of 128×128 pixels within 0.1 second required for encryption, and decryption in the presence of the channel noise. The decryption results for gray and colored images show that the system can accurately decipher the ciphered image, but with low level distortion in the image pixels due to the channel noise. These results make the proposed cryptosystem suitable for real time secure communications.</span>

Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC

A 2-then-1-bit/cycle noise-shaping successive-approximation register (SAR) analog-to-digital converter (ADC) for high sampling rate and high resolution is presented. The conversion consists of two phases of a coarse 2-bit/cycle SAR conversion for high speed and a fine 1-bit/cycle noise-shaping SAR conversion for high accuracy. The coarse conversion is performed by both voltage and time comparison for low power consumption. A redundancy after the coarse conversion corrects the error caused by a jitter noise during the time comparison. Additionally, a mismatch error between signal and reference paths is eliminated with the help of a tail-current-sharing comparator. The proposed ADC was designed in a 28 nm CMOS process, and the simulation result shows a 68.2 dB signal-to-noise distortion (SNDR) for a sampling rate of 480 MS/s and a bandwidth of 60 MHz with good energy efficiency.