An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2021.3087660 ◽

2021 ◽

pp. 1-11

Author(s):

Chuanshi Yang ◽

Erik Olieman ◽

Alphons Litjes ◽

Lei Qiu ◽

Kai Tang ◽

...

Keyword(s):

Sar Adc ◽

Mismatch Error ◽

Shaping Technique ◽

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A 98.6 dB SNDR SAR ADC with a Mismatch Error Shaping Technique Implemented with Double Sampling

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2021.3112501 ◽

2021 ◽

pp. 1-1

Author(s):

Chuanshi Yang ◽

Lei Qiu ◽

Kai Tang ◽

Yuanjin Zheng

Keyword(s):

Sar Adc ◽

Double Sampling ◽

Mismatch Error ◽

Shaping Technique

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Comparison Of Capacitive DAC Architectures for Power and Area Efficient SAR ADC Designs

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401768 ◽

2021 ◽

Author(s):

Ankita Ahuja ◽

Komail Badami ◽

Cedric Barbelenet ◽

Stephane Emery

Keyword(s):

Sar Adc ◽

Capacitive Dac ◽

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A low-cost 0.98μW0.8V oversampled SAR ADC with pre-comparison and mismatch error shaping achieving 84.5dB SNDR and 103dB SFDR

2021 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc51472.2021.9431475 ◽

2021 ◽

Author(s):

Yuting Shen ◽

Hanyue Li ◽

Haoming Xin ◽

Eugenio Cantatore ◽

Pieter Harpe

Keyword(s):

Low Cost ◽

Sar Adc ◽

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A highly energy-efficient, highly area-efficient capacitance multiplexing switching scheme for SAR ADC

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-018-1217-2 ◽

2018 ◽

Vol 96 (1) ◽

pp. 207-215 ◽

Author(s):

Jian Liu ◽

Ruixue Ding ◽

Shubin Liu ◽

Zhangming Zhu

Keyword(s):

Energy Efficient ◽

Sar Adc ◽

Switching Scheme ◽

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A low power area efficient 10-bit SAR ADC with parasitic insensitive capacitive DAC

2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS) ◽

10.1109/icmdcs.2017.8211571 ◽

2017 ◽

Author(s):

B Bibin Raj ◽

Devi Sreekumar

Keyword(s):

Low Power ◽

Sar Adc ◽

Capacitive Dac ◽

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Design of Low Power, High Speed, Low Offset and Area Efficient Dynamic-Latch Comparator for SAR-ADC

2020 International Conference on Innovative Trends in Communication and Computer Engineering (ITCE) ◽

10.1109/itce48509.2020.9047792 ◽

2020 ◽

Author(s):

Kasi Bandla ◽

Harikrishnan A. ◽

Dipankar Pal

Keyword(s):

Low Power ◽

Sar Adc ◽

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Low Energy and Area Efficient Nonbinary Capacitor Array Based SAR ADC

2014 Fifth International Symposium on Electronic System Design ◽

10.1109/ised.2014.19 ◽

2014 ◽

Author(s):

D.N. Jagadish ◽

M.S. Bhat

Keyword(s):

Sar Adc ◽

Capacitor Array ◽

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Energy and area-efficient tri-level switching procedure based on half of the reference voltage for SAR ADC

IEICE Electronics Express ◽

10.1587/elex.9.1397 ◽

2012 ◽

Vol 9 (17) ◽

pp. 1397-1401 ◽

Author(s):

Mohsen Shahmohammadi ◽

Shahin J. Ashtiani ◽

Mahmoud Kamarei

Keyword(s):

Sar Adc ◽

Reference Voltage ◽

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Area-efficient readout with 14-bit SAR-ADC for CMOS image sensors

MATEC Web of Conferences ◽

10.1051/matecconf/20167601006 ◽

2016 ◽

Vol 76 ◽

pp. 01006

Author(s):

Sassi Ben Aziza ◽

Daniel Dzahini

Keyword(s):

Image Sensors ◽

Sar Adc ◽

Cmos Image Sensors ◽

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A low-energy area-efficient dual channel SAR ADC using common capacitor array technique

2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER) ◽

10.1109/discover.2016.7806240 ◽

2016 ◽

Author(s):

N Sridhar Reddy ◽

D. N. Jagadish ◽

M. S. Bhat

Keyword(s):

Sar Adc ◽

Dual Channel ◽

Capacitor Array ◽

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