A low-cost 0.98μW0.8V oversampled SAR ADC with pre-comparison and mismatch error shaping achieving 84.5dB SNDR and 103dB SFDR

2021 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc51472.2021.9431475 ◽

2021 ◽

Author(s):

Yuting Shen ◽

Hanyue Li ◽

Haoming Xin ◽

Eugenio Cantatore ◽

Pieter Harpe

Keyword(s):

Low Cost ◽

Sar Adc ◽

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A 10-bit 320-MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20-nm CMOS

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) ◽

10.1109/asscc.2014.7008864 ◽

2014 ◽

Author(s):

Chun-Cheng Liu

Keyword(s):

Low Cost ◽

Sar Adc ◽

Ieee 802.11Ac ◽

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An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2016.2592623 ◽

2016 ◽

Vol 51 (12) ◽

pp. 2928-2940 ◽

Author(s):

Yun-Shiang Shu ◽

Liang-Ting Kuo ◽

Tien-Yu Lo

Keyword(s):

Sar Adc ◽

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A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4x Passive Gain and Second-Order DAC Mismatch Error Shaping

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2021.3087661 ◽

2021 ◽

pp. 1-1

Author(s):

Jiaxin Liu ◽

Xing Wang ◽

Zijie Gao ◽

Mingtao Zhan ◽

Xiyuan Tang ◽

...

Keyword(s):

Second Order ◽

Sar Adc ◽

Noise Shaping ◽

Mismatch Error ◽

Calibration Free ◽

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An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2021.3087660 ◽

2021 ◽

pp. 1-11

Author(s):

Chuanshi Yang ◽

Erik Olieman ◽

Alphons Litjes ◽

Lei Qiu ◽

Kai Tang ◽

...

Keyword(s):

Sar Adc ◽

Mismatch Error ◽

Shaping Technique ◽

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Small-area low-power heart condition monitoring system using dual-mode SAR-ADC for low-cost wearable healthcare systems

Technology and Health Care ◽

10.3233/thc-150963 ◽

2015 ◽

Vol 23 (s2) ◽

pp. S277-S284

Author(s):

Young-San Shin ◽

Jae-Kyung Wee ◽

Inchae Song ◽

Seongsoo Lee

Keyword(s):

Low Power ◽

Monitoring System ◽

Condition Monitoring ◽

Low Cost ◽

Healthcare Systems ◽

Sar Adc ◽

Dual Mode ◽

Condition Monitoring System ◽

Heart Condition

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A mismatch-error minimized four-channel time-interleaved 11 b 150 MS/s pipelined SAR ADC

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-013-0074-2 ◽

2013 ◽

Vol 76 (1) ◽

pp. 1-13 ◽

Author(s):

Hye-Lim Park ◽

Min-Ho Choi ◽

Sang-Pil Nam ◽

Tai-Ji An ◽

Seung-Hoon Lee

Keyword(s):

Sar Adc ◽

Mismatch Error ◽

Time Interleaved

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A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2015.2466475 ◽

2015 ◽

Vol 50 (11) ◽

pp. 2645-2654 ◽

Author(s):

Chun-Cheng Liu ◽

Che-Hsun Kuo ◽

Ying-Zu Lin

Keyword(s):

Low Cost ◽

Sar Adc ◽

Ieee 802.11Ac ◽

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A 103-dB SFDR Calibration-Free Oversampled SAR ADC With Mismatch Error Shaping and Pre-Comparison Techniques

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2021.3135559 ◽

2021 ◽

pp. 1-1

Author(s):

Yuting Shen ◽

Hanyue Li ◽

Haoming Xin ◽

Eugenio Cantatore ◽

Pieter Harpe

Keyword(s):

Sar Adc ◽

Mismatch Error ◽

Calibration Free

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27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS

2016 IEEE International Solid-State Circuits Conference (ISSCC) ◽

10.1109/isscc.2016.7418105 ◽

2016 ◽

Author(s):

Yun-Shiang Shu ◽

Liang-Ting Kuo ◽

Tien-Yu Lo

Keyword(s):

Sar Adc ◽

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A 98.6 dB SNDR SAR ADC with a Mismatch Error Shaping Technique Implemented with Double Sampling

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2021.3112501 ◽

2021 ◽

pp. 1-1

Author(s):

Chuanshi Yang ◽

Lei Qiu ◽

Kai Tang ◽

Yuanjin Zheng

Keyword(s):

Sar Adc ◽

Double Sampling ◽

Mismatch Error ◽

Shaping Technique

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