Fault-Tolerant Quasi Delay Insensitive Combinational Circuits in Commercial FPGA Devices

Author(s):  
Orlando Verducci ◽  
Duarte L. Oliveira ◽  
Robson L. Moreno
Informatics ◽  
2020 ◽  
Vol 17 (2) ◽  
pp. 71-85
Author(s):  
V. V. Sapozhnikov ◽  
Vl. V. Sapozhnikov ◽  
D. V. Efanov

Simpler than known structure of the system with error correction in calculations is proposed based on duplication and triplication of blocks with majority principle of choosing the values of signals. It is advisable to use the new fault-tolerant structure for automation devices with combinational logic. In fault-tolerant structure synthesis, the parity method is used to establish the fact of a fault in the main logic unit and the logical complement method is used determine incorrectly calculated output functions and to generate signals for their correction. The method also allows to adjust the values of incorrectly calculated functions. Structural diagram and description of error correction system are given. The synthesis algorithm of control equipment is described with minimization of the technical implementation complexity. The experiment results with control combinational circuits are given, confirming the high efficiency of proposed system structure with error correction.


2017 ◽  
Vol 8 (2) ◽  
pp. 117-126
Author(s):  
S. Meyyappan ◽  
V. Alamelumangai

The paper unveils a black box model-based self healing strategy to suppress the ill effects of stuck-at-faults occurring in combinational circuits. The primary theory endeavours to attach a sense of reliability in the performance of digital systems and makes them insensitive to the negative impact of faults present in the system. The proposed methodology employs a dynamic fault tolerant approach to protect digital systems from the incursion of stuck-at-faults and enables the system to come up with fault free outputs. The simulation results affirm the authenticity of the proposed strategy to cancel out the influence of faults and facilitate the system to heal itself. The work utilizes the attributes of an FPGA to demonstrate the practical viability of the proposed approach. The performance analysis endorses the definite dominance of the proposed healing scheme over the traditional Triple Modular Redundancy [TMR] in terms of fault coverage and area overhead.


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