scholarly journals Signal correction for combinational automation devices on the basis of Boolean complement with control of calculations by parity

Informatics ◽  
2020 ◽  
Vol 17 (2) ◽  
pp. 71-85
Author(s):  
V. V. Sapozhnikov ◽  
Vl. V. Sapozhnikov ◽  
D. V. Efanov
Keyword(s):  
Error Correction ◽  
High Efficiency ◽  
Fault Tolerant ◽  
System Structure ◽  
Combinational Circuits ◽  
Synthesis Algorithm ◽  
Majority Principle ◽  
Structure Synthesis ◽  
Signal Correction ◽  
Correction System

Simpler than known structure of the system with error correction in calculations is proposed based on duplication and triplication of blocks with majority principle of choosing the values of signals. It is advisable to use the new fault-tolerant structure for automation devices with combinational logic. In fault-tolerant structure synthesis, the parity method is used to establish the fact of a fault in the main logic unit and the logical complement method is used determine incorrectly calculated output functions and to generate signals for their correction. The method also allows to adjust the values of incorrectly calculated functions. Structural diagram and description of error correction system are given. The synthesis algorithm of control equipment is described with minimization of the technical implementation complexity. The experiment results with control combinational circuits are given, confirming the high efficiency of proposed system structure with error correction.

scholarly journals Exponential suppression of bit or phase errors with cyclic error correction

Nature ◽  
2021 ◽  
Vol 595 (7867) ◽  
pp. 383-387
Author(s):  
◽  
Zijun Chen ◽  
Kevin J. Satzinger ◽  
Juan Atalaya ◽  
Alexander N. Korotkov ◽  
...  
Keyword(s):  
Error Correction ◽  
Error Detection ◽  
Fault Tolerant ◽  
Error Rates ◽  
Quantum Error Correction ◽  
Superconducting Qubits ◽  
Two Dimensional ◽  
Logical Error ◽  
Quantum Error ◽  
Logical Qubit

AbstractRealizing the potential of quantum computing requires sufficiently low logical error rates1. Many applications call for error rates as low as 10−15 (refs. 2–9), but state-of-the-art quantum platforms typically have physical error rates near 10−3 (refs. 10–14). Quantum error correction15–17 promises to bridge this divide by distributing quantum logical information across many physical qubits in such a way that errors can be detected and corrected. Errors on the encoded logical qubit state can be exponentially suppressed as the number of physical qubits grows, provided that the physical error rates are below a certain threshold and stable over the course of a computation. Here we implement one-dimensional repetition codes embedded in a two-dimensional grid of superconducting qubits that demonstrate exponential suppression of bit-flip or phase-flip errors, reducing logical error per round more than 100-fold when increasing the number of qubits from 5 to 21. Crucially, this error suppression is stable over 50 rounds of error correction. We also introduce a method for analysing error correlations with high precision, allowing us to characterize error locality while performing quantum error correction. Finally, we perform error detection with a small logical qubit using the 2D surface code on the same device18,19 and show that the results from both one- and two-dimensional codes agree with numerical simulations that use a simple depolarizing error model. These experimental demonstrations provide a foundation for building a scalable fault-tolerant quantum computer with superconducting qubits.

scholarly journals Theory of quasi-exact fault-tolerant quantum computing and valence-bond-solid codes

2021 ◽  
Author(s):  
Dongsheng Wang ◽  
Yunjiang Wang ◽  
Ningping Cao ◽  
Bei Zeng ◽  
Raymond Lafflamme
Keyword(s):  
Error Correction ◽  
Quantum Computation ◽  
Fault Tolerant ◽  
Valence Bond ◽  
Quantum Error Correction ◽  
Quantum Codes ◽  
Error Correction Codes ◽  
Exact Quantum ◽  
Valence Bond Solid ◽  
Quantum Error

Abstract In this work, we develop the theory of quasi-exact fault-tolerant quantum (QEQ) computation, which uses qubits encoded into quasi-exact quantum error-correction codes (``quasi codes''). By definition, a quasi code is a parametric approximate code that can become exact by tuning its parameters. The model of QEQ computation lies in between the two well-known ones: the usual noisy quantum computation without error correction and the usual fault-tolerant quantum computation, but closer to the later. Many notions of exact quantum codes need to be adjusted for the quasi setting. Here we develop quasi error-correction theory using quantum instrument, the notions of quasi universality, quasi code distances, and quasi thresholds, etc. We find a wide class of quasi codes which are called valence-bond-solid codes, and we use them as concrete examples to demonstrate QEQ computation.

scholarly journals Fault Tolerant Control of PMSM Three-Phase Four-Switch Inverter

2021 ◽  
Vol 2083 (2) ◽  
pp. 022073
Author(s):  
Yuan Cao ◽  
Fuzhi Jing ◽  
Heng Wan
Keyword(s):  
Permanent Magnet ◽  
High Efficiency ◽  
Fault Tolerant ◽  
Permanent Magnet Synchronous Motor ◽  
Fault Tolerant Control ◽  
Synchronous Motor ◽  
High Power Density ◽  
Transportation Industry ◽  
Three Phase ◽  
Fast Dynamic

Abstract Permanent Magnet Synchronous Motor (Permanent Magnet Synchronous Motor, hereinafter referred to as PMSM) has the characteristics of small size, high efficiency, high power density and fast dynamic response, etc., and more and more applications in the transportation industry. This also has higher and higher requirements for the reliability and security of PMSM drivers. In this paper, the fault tolerant control strategy of PMSM based on three phase four switch inverter is proposed based on vector control and the simulation verification is carried out.

scholarly journals SOFTWARE IMPLEMENTED HARDWARE-TRANSIENT FAULTS DETECTION

2014 ◽  
pp. 26-30
Author(s):  
Goutam Kumar Saha
Keyword(s):  
Error Correction ◽  
Fault Tolerant ◽  
Low Cost ◽  
Transient Faults ◽  
Fault Tolerant System ◽  
Cost Approach ◽  
Run Time ◽  
Commodity Systems ◽  
Fail Safe ◽  
Register Error

This paper examines a software implemented self-checking technique that is capable of detecting processorregisters' hardware-transient faults. The proposed approach is intended to detect run-time transient bit-errors in memory and processor status register. Error correction is not considered here. However, this low-cost approach is intended to be adopted in commodity systems that use ordinary off-the-shelf microprocessors, for the purpose of operational faults detection towards gaining fail-safe kind of fault tolerant system.

scholarly journals A Concatenated Error-Correction System Using the $$|u|u+v|$$ Code Construction

2017 ◽  
pp. 421-431
Author(s):  
Martin Tomlinson ◽  
Cen Jung Tjhai ◽  
Marcel A. Ambroze ◽  
Mohammed Ahmed ◽  
Mubarak Jibril
Keyword(s):  
Error Correction ◽  
Code Construction ◽  
Correction System

A Fault-Tolerant Offset Algorithm for Measured Data with Defects

2014 ◽  
Vol 902 ◽  
pp. 344-350
Author(s):  
Xiang Jia Li ◽  
Ning Dai ◽  
Wen He Liao ◽  
Yu Chun Sun ◽  
Yong Bo Wang
Keyword(s):  
High Efficiency ◽  
Fault Tolerant ◽  
Engineering Application ◽  
Measured Data ◽  
Sphere Model ◽  
High Quality ◽  
Fitting Method ◽  
Enveloping Surface ◽  
Practical Engineering ◽  
Offset Surface

Offsetting of measured data, as a basic geometric operation, has already been widely used in many areas, like reverse engineering, rapid prototyping and NC machining. However, measured data always carry typical defects like caves and singular points. A fault-tolerant offset method is proposed to create the high quality offset surface of measured data with such defects. Firstly, we generated an expansion sphere model of measured data with the radius equivalent to the offset length. Secondly, using the computational geometry application of convex hull, we acquire the data of outermost enveloping surface of this expansion sphere model. Finally, we use local MLS projection fitting method to wipe out existing defects, and generate the high-quality triangular mesh surface of the offset model. The offset surface generated by this method is suitable for practical engineering application due to its high efficiency and accuracy.

A General Framework of Algorithm-Based Fault Tolerance Technique for Computing Systems

2014 ◽  
pp. 1-21 ◽  
Author(s):  
Hodjatollah Hamidi
Keyword(s):  
Fault Tolerance ◽  
Error Correction ◽  
General Framework ◽  
Fault Tolerant ◽  
Convolutional Code ◽  
Numerical Algorithms ◽  
Convolutional Codes ◽  
Computing Systems ◽  
Specific Level ◽  
Computing Paradigm

The Algorithm-Based Fault Tolerance (ABFT) approach transforms a system that does not tolerate a specific type of faults, called the fault-intolerant system, to a system that provides a specific level of fault tolerance, namely recovery. The ABFT philosophy leads directly to a model from which error correction can be developed. By employing an ABFT scheme with effective convolutional code, the design allows high throughput as well as high fault coverage. The ABFT techniques that detect errors rely on the comparison of parity values computed in two ways. The parallel processing of input parity values produce output parity values comparable with parity values regenerated from the original processed outputs and can apply convolutional codes for the redundancy. This method is a new approach to concurrent error correction in fault-tolerant computing systems. This chapter proposes a novel computing paradigm to provide fault tolerance for numerical algorithms. The authors also present, implement, and evaluate early detection in ABFT.

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