Black box model-based self healing solution for stuck-at-faults in combinational circuits

2017 ◽  
Vol 8 (2) ◽  
pp. 117-126
Author(s):  
S. Meyyappan ◽  
V. Alamelumangai

The paper unveils a black box model-based self healing strategy to suppress the ill effects of stuck-at-faults occurring in combinational circuits. The primary theory endeavours to attach a sense of reliability in the performance of digital systems and makes them insensitive to the negative impact of faults present in the system. The proposed methodology employs a dynamic fault tolerant approach to protect digital systems from the incursion of stuck-at-faults and enables the system to come up with fault free outputs. The simulation results affirm the authenticity of the proposed strategy to cancel out the influence of faults and facilitate the system to heal itself. The work utilizes the attributes of an FPGA to demonstrate the practical viability of the proposed approach. The performance analysis endorses the definite dominance of the proposed healing scheme over the traditional Triple Modular Redundancy [TMR] in terms of fault coverage and area overhead.

2021 ◽  
Author(s):  
Matteo Corno ◽  
Stefano Dattilo ◽  
Sergio Savaresi

2018 ◽  
Vol 27 (06) ◽  
pp. 1850097 ◽  
Author(s):  
Ahmad T. Sheikh ◽  
Aiman H. El-Maleh

Due to the continuous scaling of digital systems and the increased demand on low power devices, design of effective soft error tolerance techniques is of high importance to cope with the increased susceptibility of systems to soft errors and to enhance system reliability. In this work, we propose a double modular redundancy (DMR) technique that aims to achieve high reliability with reduced area overhead. Furthermore, we propose an improved application of DMR based on the use of C-element (DMR-CEL). The proposed technique is compared with Triple Modular Redundancy (TMR) technique and DMR-CEL. Simulations performed for LGSynth’91 benchmark circuits demonstrate that applying the proposed DMR technique achieves improved reliability with significantly lower area overhead than TMR without voter protection. Furthermore, improved reliability with lower area overhead is achieved by the proposed DMR technique in comparison to DMR-CEL without C-element protection. In addition, applying a recently proposed transistor sizing technique on our proposed DMR technique achieves comparable reliability to that achieved by TMR with voter protection and DMR-CEL with C-element protection with lower area overhead than TMR.


2019 ◽  
Vol 149 ◽  
pp. 318-339 ◽  
Author(s):  
Anneliese Andrews ◽  
Ahmed Alhaddad ◽  
Salah Boukhris

2017 ◽  
Vol 8 (1) ◽  
pp. 3-7 ◽  
Author(s):  
R. Şinca ◽  
CS. Szász

The paper presents a fault-tolerant digital system design and development strategy for high reliability hardware architectures implementation. Starting from the general consideration that digital hardware systems play a key role in a large scale of control systems implementation, a triple modular redundancy (TMR) solution it is proposed for development. For this reason, the well-known 1 bit majority voter configuration has been extended and generalized to the full control bus of a digital control system. Computer simulations show that the proposed hardware solution fulfills in all the theoretical expectations and it can be used for experimental tests and implementation. The presented design solution and conclusions are well suited to generalization for a wide range of fault-tolerant digital systems development ranging from reliable and safety servo control applications up to high reliability parallel and distributed computing hardware architectures.


Author(s):  
S. Meyyappan ◽  
V. Alamelumangai

<p>The paper proposes a design strategy to retain the true nature of the output in the event of occurrence of stuck at faults at the interconnect levels of digital circuits. The procedure endeavours to design a combinational architecture which includes attributes to identify stuck at faults present in the intermediate lines and involves a healing mechanism to redress the same. The simulated fault injection procedure introduces both single as well as multiple stuck-at faults at the interconnect levels of a two level combinational circuit in accordance with the directives of a control signal. The inherent heal facility attached to the formulation enables to reach out the fault free output even in the presence of faults. The Modelsim based simulation results obtained for the Circuit Under Test [CUT] implemented using a Read Only Memory [ROM], proclaim the ability of the system to survive itself from the influence of faults. The comparison made with the traditional Triple Modular Redundancy [TMR] exhibits the superiority of the scheme in terms of fault coverage and area overhead.   </p>


1988 ◽  
Vol 16 (2) ◽  
pp. 62-77 ◽  
Author(s):  
P. Bandel ◽  
C. Monguzzi

Abstract A “black box” model is described for simulating the dynamic forces transmitted to the vehicle hub by a tire running over an obstacle at high speeds. The tire is reduced to a damped one-degree-of-freedom oscillating system. The five parameters required can be obtained from a test at a given speed. The model input is composed of a series of empirical relationships between the obstacle dimensions and the displacement of the oscillating system. These relationships can be derived from a small number of static tests or by means of static models of the tire itself. The model can constitute the first part of a broader model for description of the tire and vehicle suspension system, as well as indicating the influence of tire parameters on dynamic behavior at low and medium frequencies (0–150 Hz).


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