Transient Capless Annealing of Ion-Implanted PBN LEC GaAs for Monolithic Microwave Integrated Circuits

2005 ◽  
Author(s):  
R.C. Clarke ◽  
G.W. Eldridge ◽  
S.K. Wang ◽  
W.F. Valek
1987 ◽  
Vol 93 ◽  
Author(s):  
Phillip E. Thompson ◽  
Robert G. Wilson ◽  
David C. Ingram ◽  
Peter P. Pronko

ABSTRACTHigh energy Si implantation into GaAs is of interest for the fabrication of fully implanted monolithic microwave integrated circuits. 30Si has been implanted into LEC GaAs at energies of 1, 2, 4, and 6 MeV. We have measured atomic concentration profiles using SIMS and carrier concentration profiles using an electrolytic CV procedure. Theoretical atomic profiles have been calculated using TRIM-86. Excellent SIMS dynamic range and low background (<1014/cm3) was achieved for the profiles by the use of 30Si. The range statistics and profile shape factors: Rm, Rp, ΔRp, skewness (Y1), kurtosis (B2), and maximum Si density (Nmax) have been determined from the SIMS data by applying a Pearson IV computer fitting routine. The first two moments (Rp and ΔRp) were also obtained from the carrier profiles and the theoretical profiles. The range and standard deviation obtained from each profile have a maximum difference of only 15%, and the difference is usually less than 10%. This is less than the mutual experimental uncertainty of 17%. The samples were activated using a furnace anneal (800°C, 15 min) with a Si3N4 cap and using rapid thermal anneal (1000°C, 10s) with and without a Si3N4 cap. No redistribution of Si was observed for any of the anneal conditions within experimental error.


Author(s):  
Richard G. Sartore

In the evaluation of GaAs devices from the MMIC (Monolithic Microwave Integrated Circuits) program for Army applications, there was a requirement to obtain accurate linewidth measurements on the nominal 0.5 micrometer gate lengths used to fabricate these devices. Preliminary measurements indicated a significant variation (typically 10 % to 30% but could be more) in the critical dimensional measurements of the gate length, gate to source distance and gate to drain distance. Passivation introduced a margin of error, which was removed by plasma etching. Additionally, the high aspect ratio (4-5) of the thick gold (Au) conductors also introduced measurement difficulties. The final measurements were performed after the thick gold conductor was removed and only the barrier metal remained, which was approximately 250 nanometer thick platinum on GaAs substrate. The thickness was measured using the penetration voltage method. Linescan of the secondary electron signal as it scans across the gate is shown in Figure 1.


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