Testable Design of Reversible Circuits Using Parity Preserving Gates

IEEE Design and Test ◽

10.1109/mdat.2017.2771202 ◽

2018 ◽

Vol 35 (4) ◽

pp. 56-64 ◽

Author(s):

Hari Mohan Gaur ◽

Ashutosh Kumar Singh ◽

Umesh Ghanekar

Keyword(s):

Reversible Circuits ◽

Testable Design

Download Full-text

Testable design for cell-based design ASICs and its application to VLSI image signal processor

Electronics and Communications in Japan (Part III Fundamental Electronic Science) ◽

10.1002/ecjc.4430760406 ◽

1993 ◽

Vol 76 (4) ◽

pp. 47-56

Author(s):

Hiroyuki Kawai ◽

Shin-Ichi Nakagawa ◽

Masahiko Yoshimoto ◽

Yasutaka Horiba ◽

Takuji Ogihara ◽

...

Keyword(s):

Image Signal Processor ◽

Testable Design ◽

Signal Processor

Download Full-text

Fault Masking and Diagnosis in Reversible Circuits

2011 Sixteenth IEEE European Test Symposium ◽

10.1109/ets.2011.19 ◽

2011 ◽

Author(s):

Masoud Zamani ◽

Navid Farazmand ◽

Mehdi B. Tahoori

Keyword(s):

Reversible Circuits ◽

Download Full-text

Testable design of large random access memories

Integration ◽

10.1016/0167-9260(84)90030-0 ◽

1984 ◽

Vol 2 (4) ◽

pp. 309-330 ◽

Author(s):

Kewal K. Saluja ◽

Kim Thang Le

Keyword(s):

Random Access ◽

Testable Design

Download Full-text

A testable design of logic circuits under highly observable condition

Proceedings. International Test Conference 1990 ◽

10.1109/test.1990.114116 ◽

2002 ◽

Author(s):

W. Xiaoqing ◽

K. Kinoshita

Keyword(s):

Logic Circuits ◽

Testable Design

Download Full-text

DFT with Universal Test Set for All Missing Gate Faults in Reversible Circuits

Journal of Circuits System and Computers ◽

10.1142/s0218126622501286 ◽

2021 ◽

Author(s):

Joyati Mondal ◽

Dipak Kumar Kole ◽

Hafizur Rahaman ◽

Debesh Kumar Das ◽

Bhargab B. Bhattacharya

Keyword(s):

Test Set ◽

Universal Test ◽

Reversible Circuits

Download Full-text

Delay Testable Design Using Modified Boundary Scan

Journal of The Japan Institute of Electronics Packaging ◽

10.5104/jiep.24.663 ◽

2021 ◽

Vol 24 (7) ◽

pp. 663-667

Author(s):

Hiroyuki Yotsuyanagi ◽

Masaki Hashizume

Keyword(s):

Boundary Scan ◽

Testable Design

Download Full-text

Verified Compilation of Space-Efficient Reversible Circuits

Computer Aided Verification - Lecture Notes in Computer Science ◽

10.1007/978-3-319-63390-9_1 ◽

2017 ◽

pp. 3-21 ◽

Author(s):

Matthew Amy ◽

Martin Roetteler ◽

Krysta M. Svore

Keyword(s):

Reversible Circuits

Download Full-text

Improving Synthesis of Reversible Circuits: Exploiting Redundancies in Paths and Nodes of QMDDs

Reversible Computation - Lecture Notes in Computer Science ◽

10.1007/978-3-319-59936-6_18 ◽

2017 ◽

pp. 232-247 ◽

Author(s):

Alwin Zulehner ◽

Robert Wille

Keyword(s):

Reversible Circuits

Download Full-text

Automatic Test Pattern Generation for Multiple Missing Gate Faults in Reversible Circuits

Reversible Computation - Lecture Notes in Computer Science ◽

10.1007/978-3-319-59936-6_14 ◽

2017 ◽

pp. 176-182 ◽

Author(s):

Anmol Prakash Surhonne ◽

Anupam Chattopadhyay ◽

Robert Wille

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Automatic Test Pattern Generation ◽

Automatic Test ◽

Reversible Circuits

Download Full-text

Test Pattern Generation Effort Evaluation of Reversible Circuits

Reversible Computation - Lecture Notes in Computer Science ◽

10.1007/978-3-319-59936-6_13 ◽

2017 ◽

pp. 162-175 ◽

Author(s):

Abhoy Kole ◽

Robert Wille ◽

Kamalika Datta ◽

Indranil Sengupta

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Reversible Circuits

Download Full-text