Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs

Monolithic 3D (M3D) integration provides massive vertical integration through the use of nanoscale inter-layer vias (ILVs). However, high integration density and aggressive scaling of the inter-layer dielectric make ILVs especially prone to defects. We present a low-cost built-in self-test (BIST) method that requires only two test patterns to detect opens, stuck-at faults, and bridging faults (shorts) in ILVs. We also propose an extended BIST architecture for fault detection, called Dual-BIST, to guarantee zero ILV fault masking due to single BIST faults and negligible ILV fault masking due to multiple BIST faults. We analyze the impact of coupling between adjacent ILVs arranged in a 1D array in block-level partitioned designs. Based on this analysis, we present a novel test architecture called Shared-BIST with the added functionality of localizing single and multiple faults, including coupling-induced faults. We introduce a systematic clustering-based method for designing and integrating a delay bank with the Shared-BIST architecture for testing small-delay defects in ILVs with minimal yield loss. Simulation results for four two-tier M3D benchmark designs highlight the effectiveness of the proposed BIST framework.

A High-Reliability Redundancy Scheme for Design of Radiation-Tolerant Half-Duty Limited DC-DC Converters

Redundancy techniques are commonly used to design radiation- and fault-tolerant circuits for space applications, to ensure high reliability. However, higher reliability often comes at a cost of increased usage of hardware resources. Triple Modular Redundancy (TMR) ensures full single fault masking, with a >200% power and area overhead cost. TMR/Simplex ensures full single fault masking with a slightly more complicated circuitry, inefficient use of resource and a >200% power and area overhead cost, but with higher reliability than that of TMR. In this work, a high-reliability Spatial and Time Redundancy (TR) hybrid technique, which does not abandon a working module and is applicable for radiation hardening of half-duty limited DC-DC converters, is proposed and applied to the design of a radiation-tolerant digital controller for a Dual-Switch Forward Converter. The technique has the potential of double fault masking with a <2% increase in resource overhead cost compared to TMR. Moreover, for a Simplex module failure rate, λ, of 5%, the Reliability Improvement Factor (RIF) over the Simplex system is 20.8 and 500 for the proposed technique’s two- and three-module implementations, respectively, compared to a RIF over the Simplex system of only 7.25 for TMR and 14.3 for the regular TMR/Simplex scheme.

A Fault Tolerant Voter for Approximate Triple Modular Redundancy

Approximate Triple Modular Redundancy has been proposed in the literature to overcome the area overhead issue of Triple Modular Redundancy (TMR). The outcome of TMR/Approximate TMR modules serves as the voter input to produce the final output of a system. Because the working principle of Approximate TMR conditionally allows one of the approximate modules to differ from the original circuit, it is critical for Approximate TMR that a voter not only be tolerant toward its internal faults but also toward faults that occur at the voter inputs. Herein, we present a novel compact voter for Approximate TMR using pass transistors and quadded transistor level redundancy to achieve a higher fault masking. The design also targets a better Quality of Circuit (QoC), a new metric which we have proposed for highlighting the ability of a circuit to fully mask all possible internal faults for an input vector. Comparing the fault masking features with those of existing works, the proposed voter delivered upto 45.1%, 62.5%, 26.6% improvement in Fault Masking Ratio (FMR), QoC, and reliability, respectively. With respect to the electrical characteristics, our proposed voter can achieve an improvement of up to 50% and 56% in terms of the transistor count and power delay product, respectively.

Ensuring the dependability of technical facilities through triplication and quadrupling

Redundancy, e.g. structural redundancy, is one of the primary methods of improving the dependability, ensures failsafety and fault tolerance of components, devices and systems. According to the International Patent Classification (IPC), the class of systems and methods G06F11/18 is defined as «using passive fault-masking of the redundant circuits, e.g. by quadrupling or by majority decision circuits». Obviously, «fault-masking» masks not only faults, but failures as well. The majority decision circuits (MDC) in the minimal configuration implements a «2-out-of-3» choice. According to the above definition, such redundancy should not require a special decision circuit. However, that is not always the case. In cases when the resulting signal out of a quadruple logic is delivered to, for instance, an executive device, a «3-outof-4» selection circuit is required anyway. Another dependability-improving solution is defined by class G06F 11/20, «using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements». The word «active» is missing here, thus we have active and passive fault tolerance. The paper examines passive fault tolerance that uses triplication and quadrupling and compares the respective probabilities of no-failure.The Weibull distribution is used that most adequately describes dependability in terms of radiation durability under the effects of heavy ions. It shows that in a number of cases quadrupling has a lower redundancy than triplication. A formula is proposed that describes the conditions of preferability of quadrupling at transistor level.